3.2.7. c0, Processor Feature Register 0

The purpose of Processor Feature Register 0 is to provide information about the execution state support and programmer’s model for the processor.

The Processor Feature Register 0 is:

Figure 3.4 shows the bit arrangement of the Processor Feature Register 0.

Figure 3.4. Processor Feature Register 0 format

Table 3.12 shows how the bit values correspond with the Processor Feature Register 0 functions.

Table 3.12. Processor Feature Register 0 bit functions




Reserved, RAZ.



Indicates support for Thumb Execution Environment (ThumbEE):

0x1 = Processor supports ThumbEE.



Indicates support for Jazelle extension interface:

0x1 = Jazelle extension supported.



Indicates the type of Thumb encoding that the processor supports:

0x3 = Processor supports Thumb-2 encoding with all Thumb-2 instructions.



Indicates support for ARM instruction set:

0x1, = Processor supports ARM instructions.

Table 3.13 shows the results of attempted access for each mode.

Table 3.13. Results of access to the Processor Feature Register 0[6]

Secure privilegedNonsecure privilegedSecure UserNonsecure User

[6] An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor instruction is executed.

To access the Processor Feature Register 0, read CP15 with:

MRC p15, 0, <Rd>, c0, c1, 0 ; Read Processor Feature Register 0
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