3.2.8. c0, Processor Feature Register 1

The purpose of Processor Feature Register 1 is to provide information about the execution state support and programmer’s model for the processor.

The Processor Feature Register 1 is:

Figure 3.5 shows the bit arrangement of the Processor Feature Register 1.

Figure 3.5. Processor Feature Register 1 format


Table 3.14 shows how the bit values correspond with the Processor Feature Register 1 functions.

Table 3.14. Processor Feature Register 1 bit functions

BitsFieldFunction

[31:12]

-

Reserved, RAZ.

[11:8]

Microcontroller programmer’s model

Indicates support for microcontroller programmer’s model:

0x0 = Processor does not support microcontroller programmer’s model.

[7:4]

Security extensions

Indicates support for Security Extensions Architecture v1:

0x1 = Processor supports Security Extensions Architecture v1.

[3:0]

Programmer’s model

Indicates support for standard ARMv4 programmer’s model. All processor operating modes are supported:

0x1 = Processor supports the ARMv4 model.


Table 3.15 shows the results of attempted access for each mode.

Table 3.15. Results of access to Processor Feature Register 1[7]

Secure privilegedNonsecure privilegedSecure UserNonsecure User
ReadWriteReadWriteReadWriteReadWrite
DataUndefinedDataUndefinedUndefinedUndefinedUndefinedUndefined

[7] An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor instruction is executed.


To access the Processor Feature Register 1, read CP15 with:

MRC p15, 0, <Rd>, c0, c1, 1 ; Read Processor Feature Register 1
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