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The restrictions on accesses to the APB interface are described as follows:
The system disables accesses to the memory-mapped registers based on the privilege of the memory access.
The debugger or software running on the system might lock out different parts of the register map so they cannot be accessed while the debug session is in certain states.
The APB interface does not permit accesses to registers inside the core power domain when the core powers down.
When nonprivileged software tries to access the APB interface, the system ignores or generates an abort response on the access. You must implement this restriction at the system level because the APB protocol does not have a control signal for privileged or user access. You can choose to have the system either ignore or abort the access. Although you can place additional restrictions on the memory transactions that are permitted to access the APB interface, ARM does not recommend this.
You can lock the APB interface so access to some debug registers is restricted. There are two locks:
The debug monitor can set this lock to prevent erratic software from modifying debug registers settings. See the ARM Architecture Reference Manual for more information. A debug monitor can also set this lock prior to returning control to the application, to reduce the chance of erratic code changing the debug settings. When this lock is set, writes to all debug registers are ignored, except those writes generated by the external debugger. See Lock Access Register for more information.
An OS can set this lock on the debug register map so access to some debug registers is not permitted while the OS is performing a save or restore sequence. When this lock is set, the APB interface aborts accesses to registers in the core power domain. See Operating System Lock Access Register for more information.
The state of these locks is held on debug power domain and, therefore, is not lost when the core powers down.
These locks are set to their reset values only on reset of the debug power domain (PRESETn reset).
Be sure to set the PADDR31 input signal to 1 for accesses originated from the external debugger for the Software Lock override feature to work. See Table 12.5 for more details.
If you access a reserved or unused register while any lock is set to 1, it is Unpredictable whether or not the APB interface generates an error response.
Table 12.5 shows the APB interface access permissions with relation to software lock.
Table 12.5. APB interface access with relation to software lock
| Conditions | Registers | ||
|---|---|---|---|
| PADDR31 | Lock | LAR | Other registers |
| 1[1] | X[2] | OK[3] | OK |
| 0 | 1[4] | OK | WI[5] |
| 0 | 0 | OK | OK |
[1] The PADDR31 signal is HIGH, indicating the external debugger generated the access. [2] X indicates a Don’t care condition. The outcome does not depend on this condition. [3] OK indicates that the access succeeds. [4] LSR[1] bit is set to 1. [5] WI indicates that writes are ignored, and that reads do not change the processor state. | |||
Access to registers inside the core power domain is not possible when the core powers down. The APB interface ignores accesses to powered-down registers and returns an error response, that is, PSLVERR is set to 1.
When the core powers down, the PRSR[1] sticky power down bit is set to 1. While PRSR[1] is set to 1, the APB interface also ignores accesses to registers inside the core power domain and returns an error response, that is, PSLVERR is set to 1. This bit remains set until the debugger reads the PRSR. See Device Power Down and Reset Status Register for more details.
Table 12.6 shows the behavior of APB interface accesses to debug registers with relation to power-down event.
Table 12.6. Debug registers access with relation to power-down event
| Conditions | Registers | ||||
|---|---|---|---|---|---|
| DBGPWRDWNREQ | Sticky power down | OS Lock | DIDR, ECR, DRCR | Other debug[1] | Management[2] |
| 1 | X[3] | X | OK[4] | ERR[5] | OK |
| 0[6] | 0 | 0 | OK | OK | OK |
| 0 | 0 | 1[7] | OK | ERR | OK |
| 0 | 1[8] | X | OK | ERR | OK |
[1] This column indicates
registers in the address range of [2] This column indicates
registers in the address range of [3] X indicates a Don’t care condition. The outcome does not depend on this condition. [4] OK indicates that the access succeeds. [5] ERR indicates a PSLVERR error response; written value is ignored and reads return an Unpredictable value. [6] The DBGPWRDWNREQ signal is LOW, indicating the processor is powered up. [7] 1 indicates that OSLSR[1] is set to 1. [8] 1 indicates that PRSR[1] is set to 1. | |||||
Table 12.7 shows the behavior of APB interface accesses to power management registers with relation to power-down event.
Table 12.7. Power management registers access with relation to power-down event
| Conditions | Registers | ||||
|---|---|---|---|---|---|
| DBGPWRDWNREQ | Sticky power down | OS Lock | OSLSR, PRCR, PRSR | OSLAR | OSSRR |
| 1 | X[1] | X | OK[2] | UNP[3] | UNP |
| 0[4] | 0 | 0 | OK | OK | UNP |
| 0 | 0 | 1[5] | OK | OK | OK |
| 0 | 1[6] | X | OK | OK | UNP |
[1] X indicates a Don’t care condition. The outcome does not depend on this condition. [2] OK indicates that the access succeeds. [3] UNP indicates that the access has Unpredictable results; reads return an Unpredictable value. [4] The DBGPWRDWNREQ signal is LOW, indicating the processor is powered up. [5] 1 indicates that OSLSR[1] is set to 1. [6] 1 indicates that PRSR[1] is set to 1. | |||||
Similarly to the restrictions on accesses to debug registers as described in Power down permission, the APB interface can restrict accesses to the ETM and CTI registers based on the occurrence of power-down events.
Table 12.8 shows the behavior of APB interface accesses to ETM and CTI registers with relation to power-down event.
Table 12.8. ETM and CTI registers access with relation to power-down event
| Conditions | Registers | |||||
|---|---|---|---|---|---|---|
| DBGPWRDWNREQ | OS Lock | OSLSR | OSLAR | OSSRR | Other[1] | Management[2] |
| 1 | X[3] | OK[4] | UNP[5] | UNP | ERR[6] | OK |
| 0[7] | 0 | OK | OK | UNP | OK | OK |
| 0 | 1[8] | OK | OK | OK | ERR | OK |
[1] This column indicates
registers in the address range of [2] This column indicates
registers in the address range of [3] X indicates a Don’t care condition. The outcome does not depend on this condition. [4] OK indicates that the access succeeds. [5] UNP indicates that the access has Unpredictable results; reads return an Unpredictable value. [6] ERR indicates a PSLVERR error response; written value is ignored and reads return an Unpredictable value. [7] The DBGPWRDWNREQ signal is LOW, indicating the processor is powered up. [8] 1 indicates that OSLSR[1] is set to 1. | ||||||
The OS Lock, OSLSR, OSLAR, OSSRR, and PRSR registers described in this section are all part of the ETM programmer’s model. Do not confuse these registers with the debug registers of the same name.
| Copyright © 2006-2009 ARM Limited. All rights reserved. | ARM DDI 0344I |
| Non-Confidential | |
| PDF version | |
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