3.2.12. c0, Memory Model Feature Register 1

The purpose of the Memory Model Feature Register 1 is to provide information about the memory model, memory management, cache support, and TLB operations of the processor.

The Memory Model Feature Register 1 is:

Figure 3.8 shows the bit arrangement of the Memory Model Feature Register 1.

Figure 3.8. Memory Model Feature Register 1 format


Table 3.21 shows how the bit values correspond with the Memory Model Feature Register 1 functions.

Table 3.21. Memory Model Feature Register 1 bit functions

BitsFieldFunction

[31:28]

BTB

Indicates support for branch target buffer:

0x2 = Processor does not require flushing of BTB on VA change.

[27:24]

L1 test clean operations

Indicates support for test and clean operations on data cache, Harvard or unified architecture:

0x0 = no support in processor.

[23:20]

L1 unified cache maintenance operations

Indicates support for L1 cache, all maintenance operations, unified architecture:

0x0 = no support in processor.

[19:16]

L1 Harvard cache maintenance operations

Indicates support for L1 cache, all maintenance operations, Harvard architecture.

0x0 = Processor supports:

  • invalidate instruction cache including branch target buffer

  • invalidate data cache

  • invalidate instruction and data cache including branch target buffer.

The processor does not support Harvard version.

[15:12]

L1 unified cache line maintenance operations by set and way

Indicates support for L1 cache line maintenance operations by set and way, unified architecture:

0x0 = no support in processor.

[11:8]

L1 Harvard cache line maintenance operations by set and way

Indicates support for L1 cache line maintenance operations by set and way, Harvard architecture.

0x0 = Processor supports:

  • clean data cache line by set and way

  • clean and invalidate data cache line by set and way

  • invalidate data cache line by set and way

  • invalidate instruction cache line by set and way.

[7:4]

L1 unified cache line maintenance operations by MVA

Indicates support for L1 cache line maintenance operations by MVA, unified architecture:

0x0 = no support in processor.

[3:0]

L1 Harvard cache line maintenance operations by MVA

Indicates support for L1 cache line maintenance operations by MVA, Harvard architecture.

0x0 = Processor supports:

  • clean data cache line by MVA

  • invalidate data cache line by MVA

  • invalidate instruction cache line by MVA

  • clean and invalidate data cache line by MVA

  • invalidation of branch target buffer by MVA.


Table 3.22 shows the results of attempted access for each mode.

Table 3.22. Results of access to Memory Model Feature Register 1[11]

Secure privilegedNonsecure privilegedSecure UserNonsecure User
ReadWriteReadWriteReadWriteReadWrite
DataUndefinedDataUndefinedUndefinedUndefinedUndefinedUndefined

[11] An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor instruction is executed.


To access the Memory Model Feature Register 1, read CP15 with:

MRC p15, 0, <Rd>, c0, c1, 5 ; Read Memory Model Feature Register 1
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