3.2.28. c1, Secure Configuration Register

The purpose of the Secure Configuration Register is to define:

The Secure Configuration Register is:

Figure 3.23 shows the bit arrangement of the Secure Configuration Register.

Figure 3.23. Secure Configuration Register format


Table 3.53 shows how the bit values correspond with the Secure Configuration Register functions.

Table 3.53. Secure Configuration Register bit functions

Bits

Field

Function

[31:7]

-

Reserved. UNP, SBZP.

[6]

-

Reserved, RAZ.
[5]

AW

Determines if the A bit in the CPSR can be modified when in the Nonsecure state:

0 = disable modification of the A bit in the CPSR in the Nonsecure state, reset value

1 = enable modification of the A bit in the CPSR in the Nonsecure state.

[4]

FW

Determines if the F bit in the CPSR can be modified when in the Nonsecure state:

0 = disable modification of the F bit in the CPSR in the Nonsecure state, reset value

1 = enable modification of the F bit in the CPSR in the Nonsecure state.

[3]EA

Determines External Abort behavior for Secure and Nonsecure states:

0 = branch to abort mode on an External Abort exception, reset value

1 = branch to Monitor mode on an External Abort exception.

[2]

FIQ

Determines FIQ behavior for Secure and Nonsecure states:

0 = branch to FIQ mode on an FIQ exception, reset value

1 = branch to Monitor mode on an FIQ exception.

[1]

IRQ

Determines IRQ behavior for Secure and Nonsecure states:

0 = branch to IRQ mode on an IRQ exception, reset value

1 = branch to Monitor mode on an IRQ exception.

[0]

NS bit

Defines the operation of the processor:

0 = secure, reset value

1 = nonsecure.


Note

When the core runs in Monitor mode the state is considered secure regardless of the state of the NS bit.

The permutations of the bits in the Secure Configuration Register have certain security implications. Table 3.54 shows the results for combinations of the FW and FIQ bits.

Table 3.54. Operation of the FW and FIQ bits

FWFIQFunction
10FIQs handled locally
01FIQs can be configured to give deterministic secure interrupts
11Nonsecure state able to make denial of service attack, avoid use of this function
00For Nonsecure state, avoid because the core might enter an infinite loop for nonsecure FIQ

Table 3.55 shows the results for combinations of the AW and EA bits.

Table 3.55. Operation of the AW and EA bits

AWEAFunction
10Aborts handled locally
01All external aborts trapped to Monitor mode
11All external imprecise Data Aborts trapped to Monitor mode but the Nonsecure state can hide secure aborts from the Monitor, avoid use of this function
00For Nonsecure state, avoid this because the core can unexpectedly enter an abort mode

To access the Secure Configuration Register, read or write CP15 with:

MRC p15, 0, <Rd>, c1, c1, 0 ; Read Secure Configuration Register data
MCR p15, 0, <Rd>, c1, c1, 0 ; Write Secure Configuration Register data

An attempt to access the Secure Configuration Register from any state other than secure privileged results in an Undefined Instruction exception.

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