16.2.10. Branch instructions

Any write to the PC is considered a branch. This section describes both standard B branch instructions in addition to different instruction types with the PC as the destination register. In general, branch instructions schedule very well and have very few hazards that prevent superscalar issue. There are several properties to the execution of branches that make them behave differently than other instructions.

Conditional branches

Conditional branches are executed differently than other conditional instructions. Most conditional instructions take the destination register as an additional source and the condition codes are resolved in E2. Branches do not require the destination register, PC, as an additional source because they already use the PC as a source. They are also different than normal conditional operations because the flags resolve the condition codes in E3 rather than E2. This enables the pairing of a flag setting instruction and a branch in the same cycle.

Branches with the PC as a source or destination

Using the PC as a source register does not generally result in scheduling hazards as for the case of a general-purpose register. This is because the PC values are predicted in the pipeline and are readily available to each instruction without any forwarding required. The only exception to this rule is that an instruction with a PC as a source register cannot be dual issued with an instruction that uses the PC as a destination register.

Other than the dual issue restriction, using the PC as a destination register does not result in a hazard for subsequent instructions for the same reason.

Data processing-based branches

Data processing branches can have the same data hazards of nonbranch versions of these instructions for operands other than the PC.

Load-based branches

An LDR PC or LDM PC instruction behaves like a normal load with the exception that it requires one additional cycle to execute.

Table 16.11 shows the behavior of branch instructions.

Table 16.11. Branch instructions

Shift typeCyclesSource1Source2Source3Source4Result1Result2
BCC1[Flags:E3]---R15:E4[1]-
BLCC, BLX1[Flags:E3]---R14:E3R15:E4[1]
BXCC1[Flags:E3]Rm:E2----
Data-processing branch[2]Typically 1[3][Flags:E3]---R15:E4[1]-
Load-based branch

Basic load

plus one cycle[4]

[Flags:E3]---(Rn:E2)-

[1] Branch prediction resolution in E4.

[2] ADD PC, R1, R2 and MOV PC, R4 are both examples of data-processing branches.

[3] See Data-processing instructions for more information on cycle counts and source registers.

[4] See Load/store instructions for more information on cycle counts and source registers.


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