3.2.16. c0, Instruction Set Attributes Register 1

The purpose of the Instruction Set Attributes Register 1 is to provide information about the instruction set that the processor supports beyond the basic set.

The Instruction Set Attributes Register 1 is:

Figure 3.12 shows the bit arrangement of the Instruction Set Attributes Register 1.

Figure 3.12. Instruction Set Attributes Register 1 format


Table 3.29 shows how the bit values correspond with the Instruction Set Attributes Register 1 functions.

Table 3.29. Instruction Set Attributes Register 1 bit functions

BitsFieldFunction
[31:28]Jazelle instructions

Indicates support for Jazelle instructions:

0x1 = Processor supports BXJ and J bit in PSRs.

[27:24]Interworking instructions

Indicates support for instructions that branch between ARM and Thumb code.

0x3 = Processor supports:

  • BX, and T bit in PSRs

  • BLX, and PC loads have BX behavior

  • data-processing instructions in the ARM instruction set with the PC as the destination and the S bit cleared to 0, have the BX behavior.

[23:20]Immediate instructions

Indicates support for immediate instructions:

0x1 = Processor supports immediate instructions.

[19:16]ITE instructions

Indicates support for IfThen instructions:

0x1 = Processor supports IfThen instructions.

[15:12]Extend instructions

Indicates support for sign or zero extend instructions.

0x2 = Processor supports:

  • SXTB, SXTB16, SXTH, UXTB, UXTB16, and UXTH

  • SXTAB, SXTAB16, SXTAH, UXTAB, UXTAB16, and UXTAH.

[11:8]Exception 2 instructions

Indicates support for exception 2 instructions:

0x1 = Processor supports SRS, RFE, and CPS.

[7:4]Exception 1 instructions

Indicates support for exception 1 instructions:

0x1 = Processor supports LDM(2), LDM(3) and STM(2).

[3:0]Endian instructions

Indicates support for endianness control instructions:

0x1 = Processor supports SETEND and E bit in PSRs.


Table 3.30 shows the results of attempted access for each mode.

Table 3.30. Results of access to Instruction Set Attributes Register 1[15]

Secure privilegedNonsecure privilegedSecure UserNonsecure User
ReadWriteReadWriteReadWriteReadWrite
DataUndefinedDataUndefinedUndefinedUndefinedUndefinedUndefined

[15] An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor instruction is executed.


To access the Instruction Set Attributes Register 1, read CP15 with:

MRC p15, 0, <Rd>, c0, c2, 1 ; Read Instruction Set Attributes Register 1
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