3.2.17. c0, Instruction Set Attributes Register 2

The purpose of the Instruction Set Attributes Register 2 is to provide information about the instruction set that the processor supports beyond the basic set.

The Instruction Set Attributes Register 2 is:

Figure 3.13 shows the bit arrangement for the Instruction Set Attributes Register 2.

Figure 3.13. Instruction Set Attributes Register 2 format


Table 3.31 shows how the bit values correspond with the Instruction Set Attributes Register 2 functions.

Table 3.31. Instruction Set Attributes Register 2 bit functions

BitsFieldFunction
[31:28]

Reversal

instructions

Indicates support for reversal instructions.

0x2 = Processor supports:

  • REV

  • REV16

  • REVSH

  • RBIT.

[27:24]

PSR

instructions

Indicates support for PSR instructions:

0x1 = Processor supports MRS and MSR exception return instructions for data processing.

[23:20]

Unsigned

multiply

instructions

Indicates support for advanced unsigned multiply instructions.

0x2 = Processor supports:

  • UMULL and UMLAL

  • UMAAL.

[19:16]

Signed

multiply

instructions

Indicates support for advanced signed multiply instructions.

0x3 = Processor supports:

  • SMULL and SMLAL

  • SMLABB, SMLABT, SMLALBB,SMLALBT, SMLALTB, SMLALTT, SMLATB, SMLATT, SMLAWB, SMLAWT, SMULBB, SMULBT, SMULTB, SMULTT, SMULWB, SMULWT, and Q flag in PSRs

  • SMLAD, SMLADX, SMLALD, SMLALDX, SMLSD, SMLSDX, SMLSLD, SMLSLDX, SMMLA, SMMLAR, SMMLS, SMMLSR, SMMUL, SMMULR, SMUAD, SMUADX, SMUSD, and SMUSDX.

[15:12]

Multiply

instructions

Indicates support for multiply instructions:

0x2 = Processor supports MUL, MLA, and MLS.

[11:8]

Interruptible

instructions

Indicates support for multi-access interruptible instructions:

0x0 = Processor does not support restartable LDM and STM.

[7:4]

Memory

hint

instructions

Indicates support for memory hint instructions:

0x3 = Processor supports PLD, memory hint YIELD (true NOP), and PLI (NOP).

[3:0]

Load and

store

instructions

Indicates support for load and store instructions:

0x1 = Processor supports LDRD and STRD.


Table 3.32 shows the results of attempted access for each mode.

Table 3.32. Results of access to Instruction Set Attributes Register 2[16]

Secure privilegedNonsecure privilegedSecure UserNonsecure User
ReadWriteReadWriteReadWriteReadWrite
DataUndefinedDataUndefinedUndefinedUndefinedUndefinedUndefined

[16] An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor instruction is executed.


To access the Instruction Set Attributes Register 2, read CP15 with:

MRC p15, 0, <Rd>, c0, c2, 2 ; Read Instruction Set Attributes Register 2
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