16.6. Instruction-specific scheduling for Advanced SIMD instructions

The tables in this section use the same format presented in Instruction-specific scheduling for ARM instructions and can be interpreted in the same way. The one difference between tables in this section and those in the Instruction-specific scheduling for ARM instructions is that the execution pipeline consists of stages N1-N6 instead of E1-E5.

Advanced SIMD data-processing instructions are divided into the following subcategories:

Advanced SIMD load/store permute instructions are divided into the following subcategories:

Note

This document uses the older assembler language instruction mnemonics. See Appendix B Instruction Mnemonics for information about the Unified Assembler Language (UAL) equivalents of the Advanced SIMD instruction mnemonics. See the ARM Architecture Reference Manual for more information on the UAL syntax.

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