3.2.11. c0, Memory Model Feature Register 0

The purpose of the Memory Model Feature Register 0 is to provide information about the memory model, memory management, cache support, and TLB operations of the processor.

The Memory Model Feature Register 0 is:

Figure 3.7 shows the bit arrangement of the Memory Model Feature Register 0.

Figure 3.7. Memory Model Feature Register 0 format


Table 3.19 shows how the bit values correspond with the Memory Model Feature Register 0 functions.

Table 3.19. Memory Model Feature Register 0 bit functions

BitsFieldFunction

[31:28]

-Reserved, RAZ.

[27:24]

FCSE

Indicates support for fast context switch memory mappings:

0x1 = Processor supports FCSE.

[23:20]

Auxiliary Control Register

Indicates support for Auxiliary Control Register:

0x1 = Processor supports the Auxiliary Control Register.

[19:16]

TCM

Indicates support for TCM and associated DMA:

0x0 = Processor does not support TCM and DMA.

[15:12]

Outer shareable

Indicates support for outer shareable attribute:

0x0 = Processor does not support this model.

[11:8]

Cache coherence

Indicates support for cache coherency maintenance:

0x0 = Processor does not support this model.

[7:4]

PMSA

Indicates support for Physical Memory System Architecture (PMSA):

0x0 = Processor does not support PMSA.

[3:0]

VMSA

Indicates support for Virtual Memory System Architecture (VMSA).

0x3 = Processor supports:

  • VMSA v7 including cache and TLB type register

  • Extensions to ARMv6.


Table 3.20 shows the results of attempted access for each mode.

Table 3.20. Results of access to Memory Model Feature Register 0[10]

Secure privilegedNonsecure privilegedSecure UserNonsecure User
ReadWriteReadWriteReadWriteReadWrite
DataUndefinedDataUndefinedUndefinedUndefinedUndefinedUndefined

[10] An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor instruction is executed.


To access the Memory Model Feature Register 0, read CP15 with:

MRC p15, 0, <Rd>, c0, c1, 4 ; Read Memory Model Feature Register 0
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