3.2.15. c0, Instruction Set Attributes Register 0

The purpose of the Instruction Set Attributes Register 0 is to provide information about the instruction set that the processor supports beyond the basic set.

The Instruction Set Attributes Register 0 is:

Figure 3.11 shows the bit arrangement of the Instruction Set Attributes Register 0.

Figure 3.11. Instruction Set Attributes Register 0 format

Table 3.27 shows how the bit values correspond with the Instruction Set Attributes Register 0 functions.

Table 3.27. Instruction Set Attributes Register 0 bit functions




Reserved, RAZ.


Divide instructions

Indicates support for divide instructions:

0x0 = Processor does not support divide instructions.


Debug instructions

Indicates support for debug instructions:

0x1 = Processor supports BKPT.


Coprocessor instructions

Indicates support for coprocessor instructions. This field reads as zero (RAZ).


Compare and branch instructions

Indicates support for combined compare and branch instructions:

0x1 = Processor supports combined compare and branch instructions.


Bitfield instructions

Indicates support for bitfield instructions:

0x1 = Processor supports bitfield instructions.


Bit count instructions

Indicates support for bit counting instructions:

0x1 = Processor supports CLZ.


Atomic instructions

Indicates support for atomic load and store instructions:

0x1 = Processor supports SWP and SWPB.

Table 3.28 shows the results of attempted access for each mode.

Table 3.28. Results of access to Instruction Set Attributes Register 0[14]

Secure privilegedNonsecure privilegedSecure UserNonsecure User

[14] An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor instruction is executed.

To access the Instruction Set Attributes Register 0, read CP15 with:

MRC p15, 0, <Rd>, c0, c2, 0 ; Read Instruction Set Attributes Register 0
Copyright © 2006-2009 ARM Limited. All rights reserved.ARM DDI 0344I