Cortex-A8 Technical Reference Manual: 12.5.4. Integration Input Status Register

12.5.4. Integration Input Status Register

When the processor is in integration mode, you can use the read-only Integration Input Status Register to read the state of the debug unit inputs to determine how they are connected to the CTI and to other parts of the system.

Figure 12.21 shows the bit arrangement of the Integration Input Status Register.

Figure 12.21. Integration Input Status Register format

Table 12.36 shows how the bit values correspond with the Integration Input Status Register functions.

Table 12.36. Integration Input Status Register bit functions

Bits	Field	Function
[31:12]	-	Reserved. RAZ, SBZP.
[11]	CTI DBGRESTART	CTI debug restart bit.This field reads the state of the debug restart input coming from the CTI into the Performance Monitoring Unit.
[10]	CTI EDBGRQ	CTI debug request bit. This field reads the state of the debug request input coming from the CTI into the Performance Monitoring Unit.
[9]	CTI PMUEXTIN[1]	CTI PMUEXTIN[1] signal. This field reads the state of the PMUEXTIN[1] input coming from the CTI into the Performance Monitoring Unit.
[8]	CTI PMUEXTIN[0]	CTI PMUEXTIN[0] signal. This field reads the state of the PMUEXTIN[0] input coming from the CTI into the Performance Monitoring Unit.
[7:3]	-	Reserved. RAZ, SBZP.
[2]	nFIQ	nFIQ. This field reads 1 when the nFIQ input is asserted, that is, cleared to 0.
[1]	nIRQ	nIRQ. This field reads 1when the nIRQ input is asserted, that is, cleared to 0.
[0]	EDBGRQ	EDBGRQ. This field reads the state of the EDBGRQ input.

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