3.2.55. c9, L2 Cache Auxiliary Control Register

The purpose of the L2 Cache Auxiliary Control Register is to enable you to configure the L2 cache behavior.

The L2 Cache Auxiliary Control Register is:

Note

If bit [24] of the L2 Cache Auxiliary Control Register is not set to 1, the L2 cache does not perform a security check for the data that is placed in the L2 cache. If software requires a higher level of security within the processor, then you must set bit [24] to 1 of this register. By setting bit [24] to 1, the L2 cache performs an external linefill, and the AXI slave performs the security check on that linefill.

Figure 3.49 shows the bit arrangement of the L2 Cache Auxiliary Control Register.

Figure 3.49. L2 Cache Auxiliary Control Register format


Table 3.108 shows how the bit values correspond with the L2 Cache Auxiliary Control Register functions.

Table 3.108. L2 Cache Auxiliary Control Register bit functions

BitsFieldFunction
[31:30]-Reserved. UNP, SBZP.
[29]L2 data RAM read multiplexer select

Configures the timing of the read data multiplexer select between one or two cycles for all L2 data RAM read operations:

0 = two cycles, default

1 = one cycle.

[28]ECC or Parity

Selects ECC or parity:

0 = parity

1 = ECC.

[27]Load data forwarding disable

Enables or disables load data forwarding to any LS or NEON request:

0 = enables load data forwarding, default

1 = disables load data forwarding.

[26]-Reserved. UNP, SBZP.
[25]Write combining disable

Enables or disables write combining:

0 = enables write combine, default

1 = disables write combine.

[24]Write allocate delay disable

Enables or disables external linefill when storing an entire line with write allocate permission:

0 = enables write allocate delay, default

1 = disables write allocate delay.

[23]Write allocate combine disable

Enables or disables combining of data in the L2 write combining buffers:

0 = enables write allocate combine, default

1 = disables write allocate combine.

[22]Write allocate disable

Enables or disables allocate on write miss in L2:

0 = enables write allocate, default

1 = disables write allocate.

[21]Parity or ECC enable

Parity or ECC enable:

0 = disables parity or ECC, default

1 = enables parity or ECC.

[20:17]-Reserved. UNP, SBZP.
[16]L2 inner

Defines whether the L2 observes the inner or outer cacheability attributes:

0 = L2 observes outer cacheability

1 = L2 observes inner cacheability.

[15:9]-Reserved. UNP, SBZP.
[8:6]Tag RAM latency

Program tag RAM latency:

b000 = 2 cycles

b001 = 2 cycles

b010 = 3 cycles

b011 = 4 cycles

b100 = 4 cycles

b101 = 4 cycles

b110 = 4 cycles

b111 = 4 cycles.

[5:4]-Reserved. UNP, SBZP.
[3:0]Data RAM latency

Program data RAM latency:

b0000 = 2 cycles

b0001 = 2 cycles

b0010 = 3 cycles

b0011 = 4 cycles

b0100 = 5 cycles

b0101 = 6 cycles

b0110 = 7 cycles

b0111 = 8 cycles

b1000 = 9 cycles

b1001 = 10 cycles

b1010 = 11 cycles

b1011 = 12 cycles

b1100 = 13 cycles

b1101 = 13 cycles

b1110 = 13 cycles

b1111 = 13 cycles.


Table 3.109 shows the results of attempted access for each mode.

Table 3.109. Results of access to the L2 Cache Auxiliary Control Register[45]

Secure privilegedNonsecure privilegedSecure UserNonsecure User
ReadWriteReadWriteReadWriteReadWrite
DataDataDataUndefinedUndefinedUndefinedUndefinedUndefined

[45] An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor instruction is executed.


To access the L2 Cache Auxiliary Control Register, read or write CP15 with:

MRC p15, 1, <Rd>, c9, c0, 2 ; Read L2 Cache Auxiliary Control Register
MCR p15, 1, <Rd>, c9, c0, 2 ; Write L2 Cache Auxiliary Control Register

If you have not configured the processor to include parity and ECC RAM, then software cannot set bit [21] to 1, parity or ECC enable bit. The following code sequence shows how to determine if the processor was configured to include parity and ECC RAM.

    MRC p15, 1, <Rd>, c9, c0, 2 ; Read L2 Cache Auxiliary Control Register
    ORR <Rd>, <Rd>, #0x0020_0000; Set parity/ECC enable
    MCR p15, 1, <Rd>, c9, c0, 2 ; Write L2 Cache Auxiliary Control Register
    MRC p15, 1, <Rd>, c9, c0, 2 ; Read L2 Cache Auxiliary Control Register
    TST <Rd>, #0x0020_0000 ;      Test for parity/ECC enable
    BEQ no_parity_ram_setup

parity_ram_setup:
    ;<do parity RAM setup>
    B done_parity_RAM_setup

no_parity_ram_setup:
    ;<do no parity/ECC RAM setup>

done_parity_RAM_setup:
    ;<continue>
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