16.2.8. Load/store instructions

There are many key characteristics that define different load/store instructions including the addressing mode, the data type, data size, whether or not register writeback is enabled, and indexing mode. Table 16.9 and Table 16.10 specify the timing for various load/store instruction types based on each of these characteristics, but only if that characteristic has an effect on timing. For example, data type and all data sizes except 64-bit offset do not affect instruction timing.

Table 16.9 shows the operation of load instructions.

Table 16.9. Load instructions

Addressing modeCyclesSourceResult
  1234123
Immediate offset1Rn:E1[Rd:E2]--Rd:E3(Rn:E2)-
Register offset1Rn:E1Rm:E1[Rd:E2]-Rd:E3(Rn:E2)-
Immediate 64-bit offset2Rn:E1-[Rd:E2]-Rd:E3(Rn:E2)

[Rd+1]:E3,

2nd iteration

Register 64-bit offset2Rn:E1Rm:E1[Rd:E2]-Rd:E3(Rn:E2)

[Rd+1]:E3,

2nd iteration

Scaled register offset, LSL by 21Rn:E1Rm:E1[Rd:E2]-Rd:E3(Rn:E2)-
Scaled register offset, other2Rn:E1Rm:E1[Rd:E2]-Rd:E3

(Rn:E2),

2nd iteration

-

Table 16.10 shows the operation of store instructions.

Table 16.10. Store instructions

Addressing modeCyclesSource1Source2Source3Source4Result1
Immediate offset1Rn:E1Rd:E3--(Rn:E2)
Register offset1Rn:E1Rm:E1Rd:E3-(Rn:E2)
Immediate 64-bit offset2Rn:E1Rd:E3

[Rd+1]:E3,

1st iteration

-(Rn:E2)
Register 64-bit offset2Rn:E1Rm:E1Rd:E3

[Rd+1]:E3,

1st iteration

(Rn:E2)

Scaled register offset, LSL by 2

1Rn:E1Rm:E1Rd:E3-(Rn:E2)

Scaled register offset, other

2Rn:E1Rm:E1Rd:E3-

(Rn:E2),

2nd iteration


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