12.5.3. Integration External Output Control Register

When the processor is in integration mode, you can use the read/write Integration External Output Control Register to drive certain debug unit outputs to determine how they are connected to other parts of the system.

Figure 12.20 shows the bit arrangement of the Integration External Output Control Register.

Figure 12.20. Integration External Output Control Register format


Table 12.35 shows how the bit values correspond with the Integration External Output Control Register functions.

Table 12.35. Integration External Output Control Register bit functions

BitsFieldFunction

[31:8]

-Reserved. RAZ, SBZP.

[7]

nDMAEXTERRIQ

nDMAEXTERRIRQ. This signal drives the nDMAEXTERRIRQ output. If this bit is set to 1, the corresponding internal nDMAEXTERRIRQ signal is asserted, that is, cleared to 0. The reset value is 0.

[6]

nDMASIRQ

nDMASIRQ. This signal drives the nDMASIRQ output. If this bit is set to 1, the corresponding internal nDMASIRQ signal is asserted, that is, cleared to 0. The reset value is 0.

[5]

nDMAIRQ

nDMAIRQ. This signal drives the nDMAIRQ output. If this bit is set to 1, the corresponding internal nDMAIRQ signal is asserted, that is, cleared to 0. The reset value is 0.

[4]

nPMUIRQ

nPMUIRQ. This signal drives the nPMUIRQ output. If this bit is set to 1, the corresponding internal nPMUIRQ signal is asserted, that is, cleared to 0. The reset value is 0.

[3]

STANDBYWFI

STANDBYWFI. This signal drives the STANDBYWFI output. The reset value is 0.

[2]

COMMTX

COMMTX. This signal drives the COMMTX output. The reset value is 0.

[1]

COMMRX

COMMRX. This signal drives the COMMRX output. The reset value is 0.

[0]

DBGACK

DBGACK. This signal drives the DBGACK output. The reset value is 0.


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