14.2. ETM configuration

ETMv3.3 permits a number of configurations. Table 14.1 shows the options implemented in the Cortex-A8 ETM.

Table 14.1. ETM implementation

Resource descriptionConfiguration
Instruction traceYes
Data address traceYes
Data value traceNo
Jazelle trace-
Address comparator pairs 4
Data comparators2
Context ID comparators1
Start/stop blockYes
EmbeddedICE comparators0
External inputs4
External outputs2
Extended external inputs49
Extended external input selectors 2
Instrumentation resources4
FIFOFULL level settingN/A
Branch broadcastingYes
ASIC Control Register (bits)8
Data suppressionYes
Software access to registersMemory
Readable registersYes
FIFO size128 bytes
Minimum port size32
Maximum port size32
Port modes Dynamic
Asynchronous ATB interfaceYes
Load pc firstNo
Fetch comparisonsNo

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