3.1.1. System control coprocessor functional groups

The system control coprocessor is a set of registers that you can write to and read from. Some of the registers permit more than one type of operation. The functional groups for the registers are:

The system control coprocessor controls the Security Extensions operation of the processor:


When Monitor mode is active, the core is in the Secure state. The processor treats all accesses as secure and the system control coprocessor behaves as if it operates in the Secure state regardless of the value of the NS bit, see c1, Secure Configuration Register. In Monitor mode the NS bit defines which copies of the banked registers in the system control coprocessor the processor can access:

NS = 0

Access to Secure state CP15 registers.

NS = 1

Access to Nonsecure state CP15 registers.

Registers that are only accessible in the Secure state are always accessible in Monitor mode, regardless of the value of the NS bit.

Table 3.1 shows the overall functionality of the system control coprocessor registers.

Table 3.1. System control coprocessor register functions

FunctionRegister/operationReference to description
System control and configurationControlc1, Control Register
Auxiliary Controlc1, Auxiliary Control Register
Secure Configurationc1, Secure Configuration Register
Secure Debug Enablec1, Secure Debug Enable Register
Nonsecure Access Controlc1, Nonsecure Access Control Register
Coprocessor Access Controlc1, Coprocessor Access Control Register
Secure or Nonsecure Vector Base Addressc12, Secure or Nonsecure Vector Base Address Register
Monitor Vector Base Addressc12, Monitor Vector Base Address Register
Main ID Register[1]c0, Main ID Register
Silicon ID Registerc0, Silicon ID Register
Product Featuresc0, Memory Model Feature Register 0 - c0, Instruction Set Attributes Registers 5-7
MMU control and configurationTLB Typec0, TLB Type Register
Translation Table Base 0c2, Translation Table Base Register 0
 Translation Table Base 1c2, Translation Table Base Register 1
Translation Table Base Controlc2, Translation Table Base Control Register
Domain Access Controlc3, Domain Access Control Register
Data Fault Statusc5, Data Fault Status Register
Auxiliary Fault Statusc5, Auxiliary Fault Status Registers
Instruction Fault Statusc6, Instruction Fault Address Register
Instruction Fault Addressc6, Instruction Fault Address Register
Data Fault Addressc6, Data Fault Address Register
TLB Operationsc8, TLB operations
Memory region remapc10, Memory Region Remap Registers
Context IDc13, Context ID Register
FCSE PIDc13, FCSE PID Register
Thread and Process IDc13, Thread and Process ID Registers
Cache control and configurationCache Typec0, Cache Type Register
Cache Level Identificationc0, Cache Level ID Register
Cache Size Identificationc0, Cache Size Identification Registers
Cache Size Selectionc0, Cache Size Selection Register
Cache operationsc7, Cache operations
L2 cache PreLoad Engine (PLE) control and configurationPLE Identification and Status c11, PLE Identification and Status Registers
PLE User Accessibilityc11, PLE User Accessibility Register
PLE Channel Numberc11, PLE Channel Number Register
PLE Enable c11, PLE enable commands
PLE Control c11, PLE Control Register
L2 cache PLE control and configurationPLE Internal Start Addressc11, PLE Internal Start Address Register
PLE Internal End Addressc11, PLE Internal End Address Register
PLE Channel Statusc11, PLE Channel Status Register
PLE Context IDc11, PLE Context ID Register
L1 instruction and data cache, and TLB DebugL1 instruction and data cache, BTB, GHB, and TLB Debugc15, L1 system array debug data registers
L2 unified cacheL2 unified cachec15, L2 system array debug data registers
System performance monitor Performance monitoringc9, Performance Monitor Control Register - c9, Interrupt Enable Clear Register

[1] Returns device ID code.

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