12.3.3. Coprocessor registers summary

Table 12.2 shows the valid CP14 debug instructions for accessing the debug registers. All CP14 debug instructions not listed are Undefined.

Note

The CP14 debug instructions are defined as having Opcode_1 set to 0.

Table 12.2. CP14 debug registers summary

InstructionMnemonicDescription
MRC p14, 0, <Rd>, c0, c0, 0DIDRDebug Identification Register. See CP14 c0, Debug ID Register.
MRC p14, 0, <Rd>, c1, c0, 0DRARDebug ROM Address Register. See CP14 c0, Debug ROM Address Register.
MRC p14, 0, <Rd>, c2, c0, 0DSARDebug Self Address Register. See CP14 c0, Debug Self Address Offset Register.

MRC p14, 0, <Rd>, c0, c5, 0

STC p14, c5, <addressing mode>

DTRRXData Transfer Register - Receive. See Data Transfer Register.

MCR p14, 0, <Rd>, c0, c5, 0

LDC p14, c5, <addressing mode>

DTRTXData Transfer Register - Transmit. See Data Transfer Register.

MRC p14, 0, <Rd>, c0, c1, 0

MRC p14, 0, PC, c0, c1, 0

DSCRDebug Status and Control Register. See CP14 c1, Debug Status and Control Register.

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