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Home > Debug > Debug register interface > Coprocessor registers summary |
Table 12.2 shows the valid CP14 debug instructions for accessing the debug registers. All CP14 debug instructions not listed are Undefined.
The CP14 debug instructions are defined as having Opcode_1 set to 0.
Table 12.2. CP14 debug registers summary
Instruction | Mnemonic | Description |
---|---|---|
MRC p14, 0, <Rd>, c0, c0, 0 | DIDR | Debug Identification Register. See CP14 c0, Debug ID Register. |
MRC p14, 0, <Rd>, c1, c0, 0 | DRAR | Debug ROM Address Register. See CP14 c0, Debug ROM Address Register. |
MRC p14, 0, <Rd>, c2, c0, 0 | DSAR | Debug Self Address Register. See CP14 c0, Debug Self Address Offset Register. |
| DTRRX | Data Transfer Register - Receive. See Data Transfer Register. |
| DTRTX | Data Transfer Register - Transmit. See Data Transfer Register. |
| DSCR | Debug Status and Control Register. See CP14 c1, Debug Status and Control Register. |