12.4.12. Debug Run Control Register

The DRCR requests the processor to enter or leave debug state. It also clears the sticky exception bits present in the DSCR to 0.

Figure 12.11 shows the bit arrangement of the DRCR.

Figure 12.11. Debug Run Control Register format


Table 12.21 shows how the bit values correspond with the Debug Run Control Register functions.

Table 12.21. Debug Run Control Register bit functions

BitsFieldFunction

[31:4]

-

Reserved. RAZ, SBZP.

[3]

Clear sticky pipeline advance

Clear sticky pipeline advance. Writing a 1 to this bit clears DSCR[25] to 0.

[2]

Clear sticky exceptions

Clear sticky exceptions. Writing a 1 to this bit clears DSCR[8:6] to b000.

[1]

Restart request

Restart request. Writing a 1 to this bit requests that the processor leaves debug state. This request is held until the processor exits debug state. The debugger must poll DSCR[1] to determine when this request succeeds. This bit always reads as zero. Writes are ignored when the processor is not in debug state.

[0]

Halt request

Halt request. Writing a 1 to this bit triggers a halting debug event, that is, a request that the processor enters debug state. This request is held until the debug state entry occurs. The debugger must poll DSCR[0] to determine when this request succeeds. This bit always reads as zero. Writes are ignored when the processor is already in debug state.


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