12.5. Management registers

The Management registers define the standardized set of registers that is implemented by all CoreSight components. These registers are described in this section.

Table 12.32 shows the contents of the Management registers for the debug unit.

Table 12.32. Management registers

OffsetRegister numberAccessMnemonicPower domainDescription
0xD00-0xDFC832-895R-DebugProcessor Identifier Registers. See Processor ID Registers.
0xE00-0xEF0854-956R--RAZ.
0xEF4957RWITCTRL-IOCCoreIntegration Internal Output Control Register. See Integration Internal Output Control Register.
0xEF8958RWITCTRL-EOCCoreIntegration External Output Control Register. See Integration External Output Control Register.
0xEFC959RITCTRL-ISCoreIntegration Input Status Register. See Integration Input Status Register.
0xF00960RWITCTRLCoreIntegration Mode Control Register. See Integration Mode Control Register.
0xF04-0xF9C961-999R-DebugRAZ, reserved for Management Register expansion.
0xFA01000RWCLAIMSETDebugClaim Tag Set Register. See Claim Tag Set Register.
0xFA41001RWCLAIMCLRDebugClaim Tag Clear Register. See Claim Tag Clear Register.
0xFA8-0xFBC1002-1003R--RAZ.
0xFB01004WLOCKACCESSDebugLock Access Register. See Lock Access Register.
0xFB41005RLOCKSTATUSDebugLock Status Register. See Lock Status Register.
0xFB81006RAUTHSTATUSDebugAuthentication Status Register. See Authentication Status Register.
0xFBC-0xFC41007-1009R--RAZ.
0xFC81010RDEVIDDebugRAZ, reserved for Device Identifier.
0xFCC1011RDEVTYPEDebugDevice Type Register. See Device Type Register.
0xFD0-0xFFC1012-1023R-DebugIdentification Registers. See Identification Registers.

Copyright © 2006-2009 ARM Limited. All rights reserved.ARM DDI 0344I
Non-Confidential