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12.4.19. Operating System Save and Restore Register

The OSSRR is a 32-bit read/write register that enables an operating system to save (prior to power-up) or restore (after power-down) those debug registers that reside on the core power domain while the OS lock is set.

Figure 12.16 shows the bit arrangement of the OSSRR.

Figure 12.16. OS Save and Restore Register format


Table 12.29 shows how the bit values correspond with the OS Save and Restore Register functions.

Table 12.29. OS Save and Restore Register bit functions

BitsFieldFunction

[31:0]

OS save and restore

OS save and restore. A sequence of reads from this register returns the contents of all the registers that can be saved. A sequence of writes restores the saved values. The OS must initiate the sequence by writing a 0xC5ACCE55 key to the OSLAR to set the internal pointer to the starting value. This is followed by a read from the OSSRR, and then followed by a series of reads or writes. The first OSSRR read returns the length of the rest of the sequence, that is, the number of registers to be saved or restored.

These registers are saved and restored in the following order:

  1. WCR1

  2. WCR0

  3. WVR1

  4. WVR0

  5. BCR5

  6. BCR4

  7. BCR3

  8. BCR2

  9. BCR1

  10. BCR0

  11. BVR5

  12. BVR4

  13. BVR3

  14. BVR2

  15. BVR1

  16. BVR0

  17. DTRTX

  18. DSCR

  19. DTRRX

  20. DSCCR

  21. VCR

  22. WFAR.


Note

  • If the OS issues a write to the OSSRR after the sequence has been initialized by writing the key to the OSLAR, the behavior is Unpredictable.

  • Subsequent accesses after reading the length of the sequence must be either all reads or all writes. If the OS mixes reads and writes, the result is Unpredictable. Additionally, if the OS performs more accesses than registers are in the sequence, the result is also Unpredictable.

  • This process restores only writable bits. Readable bits such as flags that reflect the processor state, are not updated. This means that, after the restore sequence, the readable bits indicate the current state of the processor rather than the state of the processor at the time the OS saved them. The only exceptions to this rule are the DSCR[30:29] and DSCR[27:26] bits, these can be restored.

  • DTRRX writes and DTRTX reads through the OSSRR do not cause the APB interface to stall regardless of the value of the DSCR[22:21] field.

  • The sequence can be abandoned and restarted from the beginning by writing the key again to the OSLAR. However, the results of accesses issued before it was abandoned are committed.

  • If this register is read or written while the core is powered-down or the OS lock is not set, the results are Unpredictable.

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