12.4.2. CP14 c0, Debug ID Register

The DIDR is a read-only register that identifies the debug architecture version and specifies the number of debug resources that the processor implements.

The Debug ID Register is:

Figure 12.2 shows the bit arrangement of the DIDR.

Figure 12.2. Debug ID Register format


Table 12.11 shows how the bit values correspond with the Debug ID Register functions.

Table 12.11. Debug ID Register bit functions

BitsFieldFunction

[31:28]

WRP

Number of Watchpoint Register Pairs.

For the processor, this field reads b0001 to indicate 2 WRPs are implemented.

[27:24]

BRP

Number of Breakpoint Register Pairs.

For the processor, this field reads b0101 to indicate 6 BRPs are implemented.

[23:20]

Context

Number of Breakpoint Register Pairs with context ID comparison capability.

For the processor, this field reads b0001 to indicate 2 BRPs have context ID capability.

[19:16]

Debug architecture version

Debug architecture version:

b0100 = ARMv7 Debug.

[15:13}

-

RAZ.

[12]

Security extensions

Security extensions bit:

0 = security extensions are not implemented

1 = security extensions implemented.

For the processor, this field reads b1 to indicate that the debug security extensions are implemented.

[11:8]

-

RAZ.

[7:4]

Variant

Implementation-defined variant number. This number is incremented on functional changes. The value matches bits [23:20] of the Main ID Register in CP15 c0. See c0, Main ID Register for more information.

[3:0]

Revision

Implementation-defined revision number. This number is incremented on bug fixes. The value matches bits [3:0] of the Main ID Register in CP15 c0. See c0, Main ID Register for more information.


To access the Debug ID Register, read CP14 c0 with:

MRC p14, 0, <Rd>, c0, c0, 0 ; Read Debug ID Register
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