12.4.8. Vector Catch Register

The processor supports efficient exception vector catching. This is controlled by the read/write Vector Catch Register as Figure 12.7 shows.

Figure 12.7. Vector Catch Register format


If one of the bits in this register is set to 1 and the corresponding vector is committed for execution, then the processor either enters debug state or takes a debug exception.

Note

  • Under this model, any kind of prefetch of an exception vector can trigger a vector catch, not only the ones caused by exception entries. An explicit branch to an exception vector might generate a vector catch debug event.

  • Catches because of bits [15:0] are only triggered when the processor is in secure state or in Monitor mode. Catches because of bits [31:25] are only triggered when the processor is in nonsecure state and not in Monitor mode.

  • If bit [28], [27], [12], [11], [4], or [3] is set to 1 while the processor is in Monitor debug mode, then the processor ignores the setting and does not generate a vector catch debug event. This prevents the processor to enter an unrecoverable state. The debugger must program these bits to zero when Monitor debug mode is selected and enabled to ensure forward-compatibility.

Table 12.17 shows the bit field definitions of the Vector Catch Register. In this table, VBAR is the CP15 Vector Base Address Register for secure, VBARNS is CP15 Vector Base Address Register for nonsecure, and MVBAR is CP15 Monitor Vector Base Address Register.

Table 12.17. Vector Catch Register bit functions

BitsAccessNormal addressHigh vectors addressFunction
[31]RWVBARNS+0x0000001C0xFFFF001CVector catch enable, FIQ in Nonsecure state. The reset value is 0.
[30]RWVBARNS+0x000000180xFFFF0018Vector catch enable, IRQ in Nonsecure state. The reset value is 0.
[29]R--Reserved. RAZ, SBZP.
[28]RWVBARNS+0x000000100xFFFF0010Vector catch enable, Data Abort in Nonsecure state. The reset value is 0.
[27]RWVBARNS+0x0000000C0xFFFF000CVector catch enable, Prefetch Abort in Nonsecure state. The reset value is 0.
[26]RWVBARNS+0x000000080xFFFF0008Vector catch enable, SVC in Nonsecure state. The reset value is 0.
[25]RWVBARNS+0x000000040xFFFF0004Vector catch enable, Undefined instruction in Nonsecure state. The reset value is 0.
[24:16]R--Reserved. RAZ, SBZP.
[15]RWMVBAR+0x0000001CMVBAR+0x0000001CVector catch enable, FIQ in Secure state. The reset value is 0.
[14]RWMVBAR+0x00000018MVBAR+0x00000018Vector catch enable, IRQ in Secure state. The reset value is 0.
[13]R--Reserved. RAZ, SBZP.
[12]RWMVBAR+0x00000010MVBAR+0x00000010Vector catch enable, Data Abort in Secure state. The reset value is 0.
[11]RWMVBAR+0x0000000CMVBAR+0x0000000CVector catch enable, Prefetch Abort in Secure state. The reset value is 0.
[10]RWMVBAR+0x00000008MVBAR+0x00000008Vector catch enable, SMC in Secure state. The reset value is 0.
[9:8]R--Reserved. RAZ, SBZP.
[7]RWVBAR+0x0000001C0xFFFF001CVector catch enable, FIQ in Secure state. The reset value is 0.
[6]RWVBAR+0x000000180xFFFF0018Vector catch enable, IRQ in Secure state. The reset value is 0.
[5]R--Reserved. RAZ, SBZP.
[4]RWVBAR+0x000000100xFFFF0010Vector catch enable, Data Abort in Secure state. The reset value is 0.
[3]RWVBAR+0x0000000C0xFFFF000CVector catch enable, Prefetch Abort in Secure state. The reset value is 0.
[2]RWVBAR+0x000000080xFFFF0008Vector catch enable, SVC in Secure state. The reset value is 0.
[1]RWVBAR+0x000000040xFFFF0004Vector catch enable, Undefined instruction in Secure state. The reset value is 0.
[0]RW0x000000000xFFFF0000Vector catch enable, Reset. The reset value is 0.

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