2.11. Addresses in a processor system

Three distinct types of address exist in the processor system:

When the core is in the Secure or Nonsecure state, the VA is Secure or Nonsecure respectively. To get the VA to PA translation, the core uses secure translation tables while it is in Secure state. Otherwise it uses the nonsecure translation tables.

Table 2.7 shows the address types in the processor system.

Table 2.7. Address types in the processor system

Processor

Caches

TLBs

AXI bus

Virtual Address

Virtual index physical tag[1]

Translates Virtual Address to Physical Address

Physical Address[2]

[1] L1 cache is virtual index physical tag.

[2] L2 cache is physical address physical tag.


This is an example of the address manipulation that occurs when the processor requests an instruction.

  1. The processor issues the VA of the instruction as the Secure or Nonsecure VA according to the state of the processor.

  2. The lower bits of the VA indexes the instruction cache. The VA is translated using the Secure or Nonsecure Process ID, CP15 c13, to the MVA, and then to PA in the Translation Lookaside Buffer (TLB). The TLB performs the translation in parallel with the cache lookup. The translation uses secure descriptors if the core is in the Secure state. Otherwise it uses the nonsecure ones.

  3. If the TLB performs a successful protection check on the MVA, and the PA tag is in the instruction cache, the instruction data is returned to the processor. For information on unsuccessful protection checks, see Aborts.

  4. The PA is passed to the L2 cache. If the L2 cache contains the physical address of the requested instruction, the L2 cache supplies the instruction data.

  5. The PA is passed to the AXI bus interface to perform an external access, in the event of a cache miss. The external access is always Nonsecure when the core is in the Nonsecure state. In the Secure state, the external access is Secure or Nonsecure according to the NS attribute value in the selected descriptor.

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