2.15.1. Exception entry and exit summary

Table 2.12 summarizes the PC value preserved in the relevant r14 on exception entry and the recommended instruction for exiting the exception handler.

Table 2.12. Exception entry and exit

Exception or entry

Return instruction

Previous state

Notes

  

ARM r14_x

Thumb r14_x

 

SVC

MOVS PC, R14_svc

PC + 4

PC+2

Where the PC is the address of the SVC, SMC, or Undefined instruction

SMC

MOVS PC, R14_mon

PC + 4

-

UNDEF

MOVS PC, R14_und

PC + 4

PC+2

PABT

SUBS PC, R14_abt, #4

PC + 4

PC+4

Where the PC is the address of instruction that had the prefetch abort

FIQ

SUBS PC, R14_fiq, #4

PC + 4

PC+4

Where the PC is the address of the instruction that was not executed because the FIQ or IRQ took priority

IRQ

SUBS PC, R14_irq, #4

PC + 4

PC+4

DABT

SUBS PC, R14_abt, #8

PC + 8

PC+8

Where the PC is the address of the load or store instruction that generated the data abort

RESET

-

-

-

The value saved in r14_svc on reset is Unpredictable

BKPT

SUBS PC, R14_abt, #4

PC + 4

PC+4

Software breakpoint


Copyright © 2006-2009 ARM Limited. All rights reserved.ARM DDI 0344I
Non-Confidential