2.15.13. Exception priorities

When multiple exceptions arise at the same time, a fixed priority system determines the order that they are handled. Table 2.13 shows the order of exception priorities.

Table 2.13. Exception priorities

PriorityException

Highest

1

Reset

2

Precise data abort

3

FIQ

4

IRQ

5

Prefetch abort

6

Imprecise data abort

Lowest

7

BKPT

Undefined instruction

SVC

SMC


Some exceptions cannot occur together:

Note

If the data abort is a precise external abort and bit [3] EA of SCR is set to 1, the processor enters Monitor mode where aborts and FIQs are disabled automatically. Therefore the processor does not proceed to FIQ vector afterwards.

Copyright © 2006-2009 ARM Limited. All rights reserved.ARM DDI 0344I
Non-Confidential