2.15.6. Aborts

An abort is an exception that indicates to the operating system that the value associated with a memory access is invalid. Attempting to access invalid instruction or data memory typically causes an abort.

An abort is either:

An internal or external abort is either:

In addition, aborts can be precise or imprecise. A precise abort occurs on the instruction associated with the access that triggers the abort exception. An imprecise abort can occur on an instruction subsequent to the instruction associated with the access that triggers the abort exception.

Note

All aborts from the TLB are internal except for aborts from translation table walks that are external precise aborts. If the EA bit is 1 for translation aborts, the core branches to Monitor mode in the same way as it does for all other external aborts. See c1, Secure Configuration Register.

IRQs are disabled when an abort occurs. When the aborts are configured to branch to Monitor mode, the FIQ is also disabled.

Prefetch abort

A prefetch abort is associated with an instruction fetch as opposed to a data access.

When a prefetch abort occurs, the processor marks the prefetched instruction as invalid, but does not take the exception until it executes the instruction. If the processor does not execute the instruction, for example because a branch occurs while it is in the pipeline, the abort does not take place.

After dealing with the cause of the abort, the handler executes the following instruction irrespective of the processor operating state:

SUBS PC,R14_abt,#4

This action restores both the PC and the CPSR, and retries the aborted instruction.

Data abort

A data abort is associated with a data access as opposed to an instruction fetch.

Data aborts on the processor can be precise or imprecise.

Internal precise data aborts are those generated by data load or store accesses that the MMU checks:

  • alignment faults

  • translation faults

  • access bit faults

  • domain faults

  • permission faults.

Note

Instruction memory system operations performed with the system control coprocessors can also generate internal precise data aborts.

Externally generated data aborts can be precise or imprecise. Two separate FSR encodings indicate if the external abort is precise or imprecise:

  • all external aborts to loads or stores to strongly ordered memory are precise

  • all external aborts to loads to the Program Counter or the CSPR are precise

  • all external aborts on the load part of a SWP are precise

  • all other external aborts are imprecise.

External aborts are supported on cacheable locations. The abort is transmitted to the processor only if the processor requests a word that had an external abort.

Precise data aborts

The state of the system presented to the abort exception handler for a precise abort is always the state for the instruction that caused the abort. It cannot be the state for a subsequent instruction. As a result, it is straightforward to restart the processor after the exception handler has rectified the cause of the abort.

The processor implements the base restored Data Abort model, which differs from the base updated Data Abort model implemented by the ARM7TDMI-S processor.

With the base restored Data Abort model, when a data abort exception occurs during the execution of a memory access instruction, the processor hardware always restores the base register to the value it contained before the instruction was executed. This removes the requirement for the Data Abort handler to unwind any base register update, that the aborted instruction might have specified. This simplifies the software Data Abort handler. See the ARM Architecture Reference Manual for more information.

After dealing with the cause of the abort, the handler executes the following return instruction, irrespective of the processor operating state at the point of entry:

SUBS PC,R14_abt,#8

This restores both the PC and the CPSR, and retries the aborted instruction.

Imprecise data aborts

The state of the system presented to the abort exception handler for an imprecise data abort can be the state for an instruction after the instruction that caused the abort. As a result, it is not often possible to restart the processor from the point at which the exception occurred.

Data aborts that occur because of watchpoints are precise.

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