2.15.7. Imprecise data abort mask in the CPSR/SPSR

An imprecise data abort caused, for example, by an external error on a write that has been held in a write buffer, is asynchronous to the execution of the causing instruction. The imprecise data abort can occur many cycles after the instruction that caused the memory access has retired. For this reason, the imprecise data abort can occur at a time that the processor is in Abort mode because of a precise data abort, or can have live state in Abort mode, but be handling an interrupt.

To avoid the loss of the Abort mode state (r14_abt and SPSR_abt) in these cases, that leads the processor to enter an unrecoverable state, the system must hold the existence of a pending imprecise data abort until a time when the Abort mode can safely be entered.

A mask is included in the CPSR to indicate that an imprecise data abort can be accepted. This bit is referred to as the A bit. The imprecise data abort causes a data abort to be taken when imprecise data aborts are not masked. When imprecise data aborts are masked, then the implementation is responsible for holding the presence of a pending imprecise data abort until the mask is cleared to 0 and the abort is taken. The A bit is set to 1 automatically on entry into Abort Mode, IRQ, and FIQ Modes, and on Reset. See the ARM Architecture Reference Manual for more information.

Note

You cannot change the CPSR A bit in the Nonsecure state if the SCR bit [5] is reset. You can change the SPSR A bit in the Nonsecure state but this does not update the CPSR if the SCR bit [5] does not permit it.

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