3.2.37. c5, Auxiliary Fault Status Registers

The Auxiliary Fault Status Register is provided for compatibility with all ARMv7-A designs. This is true for both the instruction and data auxiliary FSR. The processor always reads this as RAZ. All writes are ignored.

The Auxiliary Fault Status Register is:

Table 3.70 shows the results of attempted access for each mode.

Table 3.70. Results of access to the Auxiliary Fault Status Registers[31]

Secure privilegedNonsecure privilegedSecure User Nonsecure User
ReadWriteReadWriteReadWriteReadWrite
Secure dataSecure dataNonsecure dataNonsecure dataUndefinedUndefinedUndefinedUndefined

[31] An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor instruction is executed.


To access the Auxiliary Fault Status Registers, read or write CP15 with:

MRC p15, 0, <Rd>, c5, c1, 0; Read Data Auxiliary Fault Status Register
MCR p15, 0, <Rd>, c5, c1, 0; Write Data Auxiliary Fault Status Register
MRC p15, 0, <Rd>, c5, c1, 1; Read Instruction Auxiliary Fault Status Register
MCR p15, 0, <Rd>, c5, c1, 1; Write Instruction Auxiliary Fault Status Register

There is no physical register for Auxiliary Data Fault Status Register or Auxiliary Instruction Fault Status Register as the register is always RAZ.

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