3.2.47. c9, Performance Counter Selection Register

The purpose of the Performance Counter SELection (PMNXSEL) Register is to select a Performance Monitor Count Register.

The PMNXSEL Register is:

Figure 3.43 shows the bit arrangement of the PMNXSEL Register.

Figure 3.43. Performance Counter Selection Register format


Table 3.92 shows how the bit values correspond with the PMNXSEL Register functions.

Table 3.92. Performance Counter Selection Register bit functions

BitsFieldFunction

[31:5]

-

RAZ, SBZP.

[4:0]

SEL

Counter select:

5'b00000 = selects counter 0

5'b00001 = selects counter 1

5'b00010 = selects counter 2

5'b00011 = selects counter 3.


Any values programmed in the PMNXSEL Register other than those specified in Table 3.92 are Unpredictable.

Table 3.93 shows the results of attempted access for each mode.

Table 3.93. Results of access to the Performance Counter Selection Register[38]

 

Secure privileged

Nonsecure privileged

Secure User

Nonsecure User

EN[1]ReadWriteReadWriteReadWriteReadWrite
0

Data

Data

Data

Data

Undefined

Undefined

Undefined

Undefined

1

Data

Data

Data

Data

Data

Data

Data

Data

[38] An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor instruction is executed.

[1] The EN bit in c9, User Enable Register enables User mode access of the Performance Monitor Registers.


To access the PMNXSEL Register, read or write CP15 with:

MRC p15, 0, <Rd>, c9, c12, 5; Read PMNXSEL Register
MCR p15, 0, <Rd>, c9, c12, 5; Write PMNXSEL Register
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