3.2.32. c2, Translation Table Base Register 1

The purpose of the Translation Table Base Register 1 is to hold the physical address of the first level table. The expected use of the Translation Table Base Register 1 is for OS and I/O addresses.

The Translation Table Base Register 1 is:

Figure 3.27 shows the bit arrangement of the Translation Table Base Register 1.

Figure 3.27. Translation Table Base Register 1 format


Table 3.62 shows how the bit values correspond with the Translation Table Base Register 1 functions.

Table 3.62. Translation Table Base Register 1 bit functions

BitsFieldFunction
[31:14]Translation table base 1Holds the translation table base address, the physical address of the first level translation table.
[13:5]-Reserved. RAZ, SBZ.
[4:3]RGN

Indicates the outer cacheable attributes for translation table walking:

b00 = outer noncacheable

b01 = write-back, write allocate

b10 = write-through, no allocate on write

b11 = write-back, no allocate on write.

[2]PReserved, RAZ and ignore writes. This bit is not implemented on this processor.
[1]S

Indicates the translation table walk is to nonshared or to shared memory:

0 = nonshared

1 = shared.

[0]C

Indicates the translation table walk is inner cacheable or inner noncacheable:

0 = inner noncacheable

1 = inner cacheable.


Table 3.63 shows the results of attempted access for each mode.

Table 3.63. Results of access to the Translation Table Base Register 1[29]

Secure privilegedNonsecure privilegedSecure User Nonsecure User
ReadWriteReadWriteReadWriteReadWrite
Secure dataSecure dataNonsecure dataNonsecure dataUndefinedUndefinedUndefinedUndefined

[29] An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor instruction is executed.


A write to the Translation Table Base Register 1 updates the address of the first level translation table from the value in bits [31:14] of the written value. Bits [13:5] Should-Be-Zero. The Translation Table Base Register 1 must reside on a 16KB page boundary.

To access the Translation Table Base Register 1, read or write CP15 with:

MRC p15, 0, <Rd>, c2, c0, 1 ; Read Translation Table Base Register 1
MCR p15, 0, <Rd>, c2, c0, 1 ; Write Translation Table Base Register 1

Note

The processor cannot perform a translation table walk from L1 cache. Therefore, if C is set to 1, to ensure coherency, you must store translation tables in inner write-through memory. If you store the translation tables in an inner write-back memory region, you must clean the appropriate cache entries after modification so that the mechanism for the hardware translation table walks sees them.

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