14.4.1. ID Register

The ID Register, at offset 0x1E4, is a 32-bit read-only register that provides information about the ETM architecture version and options supported. Figure 14.2 shows the bit arrangement of the ID Register.

Figure 14.2. ID Register format


Table 14.3 shows how the bit values correspond with the ID Register functions.

Table 14.3. ID Register bit functions

BitsFieldFunction

[31:24]

Implementor

Indicates implementor, ARM:

0x41.

[23:20]

-

Reserved, RAZ.

[19]

Security Extensions support

Indicates Security Extensions support. The processor supports Security Extensions architecture. If this bit is not set to 1, then the ETM behaves as if the processor is in secure state at all times.

[18]

Thumb-2 support

All 32-bit Thumb instructions are traced as a single instruction, including BL and BLX immediate.

[17]

-

Reserved, RAZ.

[16]

Load pc first

All data transfers are traced in the same order that they appear in the ARM Architecture Reference Manual.

[15:12]

ARM core family

Indicates the Cortex-A8 processor.

[11:8]

Major ETM architecture version

Indicates the major ETM architecture version number, ETMv3.

[7:4]

Minor ETM architecture version

Indicates the minor ETM architecture version number, ETMv3.3.

[3:0]

Revision

Indicates the implementation revision.


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