3.2.43. c9, Count Enable Set Register

The purpose of the CouNT ENable Set (CNTENS) Register is to enable or disable any of the Performance Monitor Count Registers.

When reading this register, any enable that reads as 0 indicates the counter is disabled. Any enable that reads as 1 indicates the counter is enabled.

When writing this register, any enable written with a value of 0 is ignored, that is, not updated. Any enable written with a value of 1 indicates the counter is enabled.

The CNTENS Register is:

Figure 3.39 shows the bit arrangement of the CNTENS Register.

Figure 3.39. Count Enable Set Register format


Table 3.84 shows how the bit values correspond with the CNTENS Register functions.

Table 3.84. Count Enable Set Register bit functions

BitsFieldFunction

[31]

C

Enable cycle counter.

[30:4]

-

Reserved. UNP, SBZ.

[3]

P3

Enable Counter 3.

[2]

P2

Enable Counter 2.

[1]

P1

Enable Counter 1.

[0]

P0

Enable Counter 0.


Table 3.85 shows the results of attempted access for each mode.

Table 3.85. Results of access to the Count Enable Set Register[35]

 

Secure privileged

Nonsecure privileged

Secure User

Nonsecure User

EN[1]ReadWriteReadWriteReadWriteReadWrite
0DataDataDataData

Undefined

Undefined

Undefined

Undefined

1DataDataDataDataDataDataDataData

[35] An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor instruction is executed.

[1] The EN bit in c9, User Enable Register enables User mode access of the Performance Monitor Registers.


To access the CNTENS Register, read or write CP15 with:

MRC p15, 0, <Rd>, c9, c12, 1 ; Read CNTENS Register
MCR p15, 0, <Rd>, c9, c12, 1 ; Write CNTENS Register
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