Cortex-A8 Technical Reference Manual: 3.2.33. c2, Translation Table Base Control Register

3.2.33. c2, Translation Table Base Control Register

The purpose of the Translation Table Base Control Register is to determine if a translation table miss for a specific VA uses, for its translation table walk, either:

Translation Table Base Register 0. The recommended use is for task-specific addresses
Translation Table Base Register 1. The recommended use is for operating system and I/O addresses.

Figure 3.28 shows the bit arrangement of the Translation Table Base Control Register.

Figure 3.28. Translation Table Base Control Register format

Table 3.64 shows how the bit values correspond with the Translation Table Base Control Register functions.

Table 3.64. Translation Table Base Control Register bit functions

Bits	Field	Function
[31:6]	-	Reserved. UNP, SBZ.
[5]	PD1	Specifies occurrence of a translation table walk on a TLB miss when using Translation Table Base Register 1. When translation table walk is disabled, a section translation fault occurs instead on a TLB miss: 0 = The processor performs a translation table walk on a TLB miss, with secure or nonsecure privilege appropriate to the current Secure or Nonsecure state. This is the reset value. 1 = The processor does not perform a translation table walk. If a TLB miss occurs with Translation Table Base Register 1 in use, the processor returns a section translation fault.
[4]	PD0	Specifies occurrence of a translation table walk on a TLB miss when using Translation Table Base Register 0. When translation table walk is disabled, a section translation fault occurs instead on a TLB miss: 0 = The processor performs a translation table walk on a TLB miss, with secure or nonsecure privilege appropriate to the current Secure or Nonsecure state. This is the reset value. 1 = The processor does not perform a translation table walk. If a TLB miss occurs with Translation Table Base Register 0 in use, the processor returns a section translation fault.
[3]	-	Reserved. UNP, SBZ.
[2:0]	N	Specifies the boundary size of Translation Table Base Register 0: b000 = 16KB, reset value b001 = 8KB b010 = 4KB b011 = 2KB b100 = 1KB b101 = 512B b110 = 256B b111 = 128B.

Attempts to write to this register in secure privileged mode when CP15SDISABLE is HIGH result in an Undefined Instruction exception, see Security Extensions write access disable.

Table 3.65 shows the results of attempted access for each mode.

Table 3.65. Results of access to the Translation Table Base Control Register

Secure privileged		Nonsecure privileged		Secure User		Nonsecure User
Read	Write	Read	Write	Read	Write	Read	Write
Secure data	Secure data	Nonsecure data	Nonsecure data	Undefined^[1]	Undefined	Undefined	Undefined
^[1]The access gives an Undefined Instruction exception when the coprocessor instruction is executed.

To access the Translation Table Base Control Register, read or write CP15 with:

MRC p15, 0, <Rd>, c2, c0, 2 ; Read Translation Table Base Control Register

MCR p15, 0, <Rd>, c2, c0, 2 ; Write Translation Table Base Control Register

A translation table base register is selected in the following fashion:

If N is set to 0, always use Translation Table Base Register 0. This is the default case at reset. It is backwards compatible with ARMv5 and earlier processors.
If N is set to a value greater than 0, and bits [31:32-N] of the VA are all zeros, use Translation Table Base Register 0. Otherwise, use Translation Table Base Register 1. N must be in the range 0-7.

Note

The processor cannot perform a translation table walk from L1 cache. Therefore, if C is set to 1, to ensure coherency, you must store translation tables in inner write-through memory. If you store the translation tables in an inner write-back memory region, you must clean the appropriate cache entries after modification so that the mechanism for the hardware translation table walks sees them.

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