3.2.58. c10, Memory Region Remap Registers

The purpose of the Memory Region Remap Registers is to remap memory region attributes encoded by the TEX[2:0], C, and B bits in the translation tables that the data side, instruction side, and PLE use. See MMU software-accessible registers for information on memory remap.

The Memory Region Remap Registers are:

These registers apply to all memory accesses and this includes accesses from the data side, instruction side, and PLE. Table 3.113 shows the purposes of the individual bits in the Primary Region Remap Register. Table 3.115 shows the purposes of the individual bits in the Normal Memory Remap Register.

Note

The behavior of the Memory Region Remap Registers depends on the TEX Remap bit, see c1, Control Register.

Table 3.112 describes the behavior of memory accesses when the region remapped registers, PRRR and NMRR, are applied.

Table 3.112. Application of remapped registers on memory access

CP15 M bitCP15 TRE bitExpected behavior
00Memory accesses are controlled by the remapped default memory attributes as defined in the ARM Architecture Reference Manual
01Memory accesses are not remapped but used the default memory attributes
10Memory accesses are not remapped and are controlled by the MMU translation table descriptors
11Memory accesses are controlled by the remapped MMU translation table descriptors

Figure 3.51 shows the bit arrangement of the Primary Region Remap Register.

Figure 3.51. Primary Region Remap Register format


Table 3.113 shows how the bit values correspond with the Primary Region Remap Register functions.

Table 3.113. Primary Region Remap Register bit functions

Bits

FieldFunction[1]
[31:20]-

Reserved. UNP, SBZ

[19]-

Remaps shareable attribute when S=1 for Normal regions[2]

1 = reset value

[18]-

Remaps shareable attribute when S=0 for Normal regionsb

0 = reset value

[17]-

Remaps shareable attribute when S=1 for Device regionsb

0 = reset value

[16]-

Remaps shareable attribute when S= 0 for Device regionsb

1= reset value

[15:14]-

Remaps {TEX[0],C,B} = b111

b10 = reset value

[13:12]-

Remaps {TEX[0],C,B} = b110

b00 = reset value

[11:10]-

Remaps {TEX[0],C,B} = b101

b10 = reset value

[9:8]-

Remaps {TEX[0],C,B} = b100

b10 = reset value

[7:6]-

Remaps {TEX[0],C,B} = b011

b10 = reset value

[5:4]-

Remaps {TEX[0],C,B} = b010

b10 = reset value

[3:2]-

Remaps {TEX[0],C,B} = b001

b01 = reset value

[1:0]-

Remaps {TEX[0],C,B} = b000

b00 = reset value

[1] The reset values ensure that no remapping occurs at reset.

[2] Shareable attributes can map for both shared and nonshared memory. If the shared bit read from the TLB or translation tables is 0, then the bit remaps to the nonshared attributes in this register. If the shared bit read from the TLB or translation tables is 1, then the bit remaps to the shared attributes of this register.


Table 3.114 shows the encoding of the remapping for the primary memory type.

Table 3.114. Encoding for the remapping of the primary memory type

EncodingMemory type
b00Strongly ordered
b01Device
b10Normal
b11UNP (Normal)

Figure 3.52 shows the bit arrangement of the Normal Memory Remap Register.

Figure 3.52. Normal Memory Remap Register format


Table 3.115 shows how the bit values correspond with the Normal Memory Remap Register functions.

Table 3.115. Normal Memory Remap Register bit functions

Bits

Field

Function[1]
[31:30]-

Remaps outer attribute for {TEX[0],C,B} = b111

b01 = reset value

[29:28]-

Remaps outer attribute for {TEX[0],C,B} = b110

b00 = reset value

[27:26]-

Remaps outer attribute for {TEX[0],C,B} = b101

b01 = reset value

[25:24]-

Remaps outer attribute for {TEX[0],C,B} = b100

b00 = reset value

[23:22]-

Remaps outer attribute for {TEX[0],C,B} = b011

b11 = reset value

[21:20]-

Remaps outer attribute for {TEX[0],C,B} = b010

b10 = reset value

[19:18]-

Remaps outer attribute for {TEX[0],C,B} = b001

b00 = reset value

[17:16]-

Remaps outer attribute for {TEX[0],C,B} = b000

b00 = reset value

[15:14]-

Remaps inner attribute for {TEX[0],C,B} = b111

b01 = reset value

[13:12]-

Remaps inner attribute for {TEX[0],C,B} = b110

b00 = reset value

[11:10]-

Remaps inner attribute for {TEX[0],C,B} = b101

b10 = reset value

[9:8]-

Remaps inner attribute for {TEX[0],C,B} = b100

b00 = reset value

[7:6]-

Remaps inner attribute for {TEX[0],C,B} = b011

b11 = reset value

[5:4]-

Remaps inner attribute for {TEX[0],C,B} = b010

b10 = reset value

[3:2]-

Remaps inner attribute for {TEX[0],C,B} = b001

b00 = reset value

[1:0]-

Remaps inner attribute for {TEX[0],C,B} = b000

b00 = reset value

[1] The reset values ensure that no remapping occurs at reset.


Table 3.116 shows the encoding for the inner or outer cacheable attribute bit fields I0 to I7 and O0 to O7.

Table 3.116. Remap encoding for inner or outer cacheable attributes

EncodingCacheable attribute
b00Noncacheable
b01Write-back, allocate on write
b10Write-through, no allocate on write
b11Write-back, no allocate on write

Attempts to write to this register in secure privileged mode when CP15SDISABLE is HIGH result in an Undefined Instruction exception, see Security Extensions write access disable.

Table 3.117 shows the results of attempted access for each mode.

Table 3.117. Results of access to the memory region remap registers[47]

Secure privilegedNonsecure privilegedSecure UserNonsecure User
ReadWriteReadWriteReadWriteReadWrite
Secure dataSecure dataNonsecure dataNonsecure dataUndefinedUndefinedUndefinedUndefined

[47] An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor instruction is executed.


To access the Memory Region Remap Registers read or write CP15 with:

MRC p15, 0, <Rd>, c10, c2, 0 ; Read Primary Region Remap Register
MCR p15, 0, <Rd>, c10, c2, 0 ; Write Primary Region Remap Register
MRC p15, 0, <Rd>, c10, c2, 1 ; Read Normal Memory Remap Register
MCR p15, 0, <Rd>, c10, c2, 1 ; Write Normal Memory Remap Register

Memory remap occurs in two stages:

  1. The processor uses the Primary Region Remap Register to remap the primary memory type, normal, device, or strongly ordered, and the shareable attribute.

  2. For memory regions that the Primary Region Remap Register defines as Normal memory, the processor uses the Normal Memory Remap Register to remap the inner and outer cacheable attributes.

The behavior of the Memory Region Remap Registers depends on the TEX Remap bit, see c1, Control Register. If the TEX Remap bit is set to 1, the entries in the Memory Region Remap Registers remap each possible value of the TEX[0], C and B bits in the translation tables. You can therefore set your own definitions for these values. If the TEX Remap bit is cleared to 0, the Memory Region Remap Registers are not used and no memory remapping takes place. See MMU software-accessible registers for more information.

The Memory Region Remap Registers are expected to remain static during normal operation. When you write to the Memory Region Remap Registers, you must invalidate the TLB and perform an IMB operation before you can rely on the new written values. You must also stop the PLE if it is running.

Note

For security reasons, you cannot remap the NS bit.

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