14.4.2. Configuration Code Register

The Configuration Code Register, at offset 0x004, is a 32-bit read-only register that provides information about the configuration of the ETM. Figure 14.3 shows the bit arrangement for the Configuration Code Register.

Figure 14.3. Configuration Code Register format


Table 14.4 shows how the bit values correspond with the Configuration Code Register functions. The Configuration Code Register has the value 0x8D294024.

Table 14.4. Configuration Code Register bit functions

BitsFieldFunction

[31]

ID Register

Indicates that the ETM ID Register is present

[30:28]

-

Reserved, RAZ

[27]

Software access

Indicates that software access is supported

[26]

Trace stop/start block

Indicates that the trace start/stop block is present

[25:24]

Number of Context ID comparators

Specifies the number of Context ID comparators

[23]

FIFOFULL logic

Indicates that it is not possible to stall the processor to prevent FIFO overflow, uses data suppression instead

[22:20]

Number of external outputs

Specifies the number of external outputs

[19:17]

Number of external inputs

Specifies the number of external inputs

[16]

Sequencer

Indicates that the sequencer is present

[15:13]

Number of counters

Specifies the number of counters

[12:8]

Number of memory map decoders

Specifies the number of memory map decoders

[7:4]

Number of data comparators

Specifies the number of data comparators

[3:0]

Number of pairs of address comparators

Specifies the number of pairs of address comparators


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