3.2.52. c9, Interrupt Enable Set Register

The purpose of the INTerrupt ENable Set (INTENS) Register is to determine if any of the Performance Monitor Count Registers, PMCNT0-PMCNT3 and CCNT, generate an interrupt on overflow.

The INTENS Register is:

When reading this register, any interrupt overflow enable bit that reads as 0 indicates the interrupt overflow flag is disabled. Any interrupt overflow enable bit that reads as 1 indicates the interrupt overflow flag is enabled.

When writing this register, any interrupt overflow enable bit written with a value of 0 is ignored, that is, not updated. Any interrupt overflow enable bit written with a value of 1 sets the interrupt overflow enable bit.

Figure 3.46 shows the bit arrangement of the INTENS Register.

Figure 3.46. Interrupt Enable Set Register format


Table 3.102 shows how the bit values correspond with the INTENS Register functions.

Table 3.102. Interrupt Enable Set Register bit functions

BitsFieldFunction
[31]C

CCNT overflow interrupt enable.

[30:4]-Reserved. UNP, SBZP.

[3]

P3

PMCNT3 overflow interrupt enable.

[2]

P2

PMCNT2 overflow interrupt enable.

[1]

P1

PMCNT1 overflow interrupt enable.

[0]

P0

PMCNT0 overflow interrupt enable.


Table 3.103 shows the results of attempted access for each mode.

Table 3.103. Results of access to the Interrupt Enable Set Register[42]

 

Secure privileged

Nonsecure privileged

Secure User

Nonsecure User

ENReadWriteReadWriteReadWriteReadWrite
0DataDataDataData

Undefined

Undefined

Undefined

Undefined

1DataDataDataData

Undefined

Undefined

Undefined

Undefined

[42] An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor instruction is executed.


To access the INTENS Register, read or write CP15 with:

MRC p15, 0, <Rd>, c9, c14, 1 ; Read INTENS Register
MCR p15, 0, <Rd>, c9, c14, 1 ; Write INTENS Register
Copyright © 2006-2009 ARM Limited. All rights reserved.ARM DDI 0344I
Non-Confidential