3.2.26. c1, Auxiliary Control Register

The purpose of the Auxiliary Control Register is to control processor-specific features that are not architecturally described.

The Auxiliary Control Register is:

Figure 3.21 shows the bit arrangement of the Auxiliary Control Register.

Figure 3.21. Auxiliary Control Register format


Table 3.49 shows how the bit values correspond with the Auxiliary Control Register functions.

Table 3.49. Auxiliary Control Register bit functions

BitsFieldSecurity StateFunction
  NSS 

[31]

L2 hardware reset disable

RAZ

R

Monitors the L2 hardware reset disable bit, L2RSTDISABLE:

0 = the L2 valid RAM contents are reset by hardware

1 = the L2 valid RAM contents are not reset by hardware.

[30]

L1 hardware reset disable

RAZ

R

Monitors the L1 hardware reset disable bit, L1RSTDISABLE:

0 = the L1 valid RAM contents are reset by hardware

1 = the L1 valid RAM contents are not reset by hardware.

[29:21]-

R

R/W

Reserved. UNP, SBZP.
[20]Cache maintenance pipelineRR/W

Specify pipelining of CP15 data cache maintenance operations. CP15 data cache clean and invalidate or data cache invalidate operations can be executed by the processor in a pipelined fashion.

0 = pipelined cache maintenance operations, reset value

1 = non-pipelined cache maintenance operations.

[19]Clock stop request disableRR/W

Disables CLKSTOPREQ:

0 = CLKSTOPREQ causes the processor to stop the internal clocks and to assert the CLKSTOPACK output, reset value

1 = disables the CLKSTOPREQ functionality.

[18]CP14/CP15 instruction serializationRR/W

Some CP14 and CP15 instructions execute natively in a serial manner. This control bit imposes serialization on those CP14 and CP15 instructions that are not natively serialized:

0 = does not enforce serialization of CP14 or CP15 instructions, reset value

1 = enforces serialization of CP14 and CP15 instructions.

[17]CP14/CP15 wait on idleRR/W

Some CP14 or CP15 instructions that execute in a serial manner require that all outstanding memory accesses complete before execution of the instruction. This control bit imposes wait on idle protocol of CP14 and CP15 serialized instructions that do not natively wait on idle:

0 = does not enforce wait on idle of CP14 and CP15 instructions, reset value

1 = enforces wait on idle for serialized CP14 or CP15 instructions.

[16]CP14/CP15 pipeline flushRR/W

After execution of some CP14 or CP15 instructions, the processor natively performs a pipeline flush before it executes the next instructions. This control bit imposes a pipeline flush on CP14 and CP15 instructions that do not natively include one:

0 = does not impose a pipeline flush on CP14 or CP15 instructions, reset value

1 = imposes a pipeline flush on CP14 and CP15 instructions.

[15]

Force ETM clock

R

R/W

Forces ETM clock enable active:

0 = does not prevent the processor clock generator from stopping the ETM clock, reset value

1 = prevents the processor clock generator from stopping the ETM clock.

[14]

Force NEON clock

R

R/W

Forces NEON clock enable active:

0 = does not prevent the processor clock generator from stopping the NEON clock, reset value

1 = prevents the processor clock generator from stopping the NEON clock.

[13]

Force main clock

R

R/W

Forces the main processor clock enable active:

0 = does not prevent the processor clock generator from stopping the main clock, reset value

1 = prevents the processor clock generator from stopping the main clock.

[12]

Force NEON single issue

R

R/W

Forces single issue of Advanced SIMD instructions:

0 = does not force single issue of Advanced SIMD instructions, reset value

1 = forces single issue of Advanced SIMD instructions.

[11]

Force load/store single issue

R

R/W

Forces single issue of load/store instructions:

0 = does not force single issue of load/store instructions, reset value

1 = forces single issue of load/store instructions.

[10]

Force single issue

R

R/W

Forces single issue of all instructions:

0 = does not force single issue of all instructions, reset value

1 = forces single issue of all instructions.

[9]

PLDNOP

R

R/W

Executes PLD instructions as a NOP instruction:

0 = PLD instructions behave as defined in the ARM Architecture Reference Manual, reset value

1 = PLD instructions are executed as NOP instructions.

The PLD instruction acts as a hint to the memory system. If the PLDNOP is set to 0, the processor performs a memory access for the PLD instruction. If the PLDNOP is set to 1, the processor does not perform a memory access. See the ARM Architecture Reference Manual for more information on the PLD instruction.

[8]

WFINOP

R

R/W

Executes WFI instructions as a NOP instruction:

0 = executes WFI instructions as defined in the ARM Architecture Reference Manual, reset value

1 = executes WFI instructions as NOP instruction.

The WFI instruction places the processor in a low-power state and stops it from executing any more until an interrupt or a debug request occurs. If the WFINOP is set to 0, then the WFI instruction places the processor in a low-power state. If the WFINOP is set to 1, the WFI instruction is executed as a NOP and does not place the processor in a low-power state. See the ARM Architecture Reference Manual for more information on the WFI instruction.

[7]

Disable branch size mispredicts

R

R/W

Prevents BTB branch size mispredicts:

0 = enables BTB branch size mispredicts, reset value

1 = executes the CP15 Invalidate All and Invalidate by MVA instructions as specified and prevents BTB branch size mispredicts.

[6]

IBE

R

R/W

Invalidates BTB enable:

0 = executes the CP15 Invalidate All and Invalidate by MVA instructions as a NOP instruction, reset value

1 = executes the CP15 Invalidate All and Invalidate by MVA instructions as specified.

[5]

L1NEON

R

R/W

Enables caching NEON data within the L1 data cache:

0 = disables caching NEON data within the L1 data cache, reset value

1 = enables caching NEON data within the L1 data and L2 cache.

Note

NEON L1 caching should be enabled for best performance when the L2 cache is off or not present.

[4]

ASA

R

R/W

Enables speculative accesses on AXI:

0 = disables speculative accesses, reset value

1 = enables speculative accesses.

[3]

L1PE

R

R/W

Enables L1 cache parity detection:

0 = L1 cache parity disabled for both instruction and data caches, reset value

1 = L1 cache parity enabled.

[2]

-

R

R/W

Reserved. UNP, SBZ.

[1]

L2EN

B

B

Enables L2 cache:

0 = L2 cache disabled

1 = L2 cache enabled. See Table 3.48 for details.

[0]

L1ALIAS

R

R/W

Enables L1 data cache hardware alias checks:

0 = L1 data cache hardware alias support enabled, reset value

1 = L1 data cache hardware alias support disabled.


Table 3.50 shows the results of attempted access for each mode.

Table 3.50. Results of access to the Auxiliary Control Register[24]

Secure privilegedNonsecure privilegedSecure UserNonsecure User
ReadWriteReadWriteReadWriteReadWrite

Data

Data

Data

Banked Data

Undefined

Undefined

Undefined

Undefined

[24] An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor instruction is executed.


To access the Auxiliary Control Register you must use a read modify write technique. To access the Auxiliary Control Register, read or write CP15 with:

MRC p15, 0, <Rd>, c1, c0, 1 ; Read Auxiliary Control Register
MCR p15, 0, <Rd>, c1, c0, 1 ; Write Auxiliary Control Register
Copyright © 2006-2009 ARM Limited. All rights reserved.ARM DDI 0344I
Non-Confidential