3.2.50. c9, Performance Monitor Count Registers

There are four Performance Monitor CouNT (PMCNT0-PMCNT3) Registers in the processor. The purpose of each PMCNT Register, as selected by the PMNXSEL Register, is to count instances of an event selected by the EVTSEL Register. Bits [31:0] of each PMCNT Register contain an event count.

The PMCNT0-PMCNT3 Registers are:

Table 3.98 shows the results of attempted access for each mode.

Table 3.98. Results of access to the Performance Monitor Count Registers[41]

 

Secure privileged

Nonsecure privileged

Secure User

Nonsecure User

EN[1]ReadWriteReadWriteReadWriteReadWrite
0DataDataDataData

Undefined

Undefined

Undefined

Undefined

1DataDataDataDataDataDataDataData

[41] An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor instruction is executed.

[1] The EN bit in c9, User Enable Register enables User mode access of the Performance Monitor Registers.


To access the PMCNT Registers, read or write CP15 with:

MRC p15, 0, <Rd>, c9, c13, 2; Read PMCNT0-PMCNT3 Registers
MCR p15, 0, <Rd>, c9, c13, 2; Write PMCNT0-PMCNT3 Registers

Table 3.99 shows what signal settings are required and the Secure or Nonsecure state and mode that you can enable the counters.

Table 3.99. Signal settings for the Performance Monitor Count Registers

DBGEN || NIDENSPIDEN || SPNIDENSUNIDENSecure stateUser modePMNC[5]Performance counters enabledCCNT enabled
0----b0NoYes
0----b1NoNo
1--No--YesYes
1--Yes--YesYes
10-YesNob0NoYes
10-YesNob1NoNo
100YesYesb0NoYes
100YesYesb1NoNo
1 01YesYesXYesYes

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