3.2.44. c9, Count Enable Clear Register

The purpose of the CouNT ENable Clear (CNTENC) Register is to enable or disable any of the Performance Monitor Count Registers.

When reading this register, any enable that reads as 0 indicates the counter is disabled. Any enable that reads as 1 indicates the counter is enabled.

When writing this register, any enable written with a value of 0 is ignored, that is, not updated. Any enable written with a value of 1 clears the counter enable to 0.

The CNTENC Register is:

Figure 3.40 shows the bit arrangement of the CNTENC Register.

Figure 3.40. Count Enable Clear Register format


Table 3.86 shows how the bit values correspond with the CNTENC Register functions.

Table 3.86. Count Enable Clear Register bit functions

BitsFieldFunction

[31]

C

Disable cycle counter.

[30:4]

-

Reserved. UNP, SBZP.

[3]

P3

Disable Counter 3.

[2]

P2

Disable Counter 2.

[1]

P1

Disable Counter 1.

[0]

P0

Disable Counter 0.


Table 3.87 shows the results of attempted access for each mode.

Table 3.87. Results of access to the Count Enable Clear Register

 

Secure privileged

Nonsecure privileged

Secure User

Nonsecure User

 ReadWriteReadWriteReadWriteReadWrite
EN = 0[1]

Data

Data

Data

Data

Undefined[2]

Undefined

Undefined

Undefined

EN = 1

Data

Data

Data

Data

Data

Data

Data

Data

[1] The EN bit in c9, User Enable Register enables User mode access of the Performance Monitor Registers.

[2] The access gives an Undefined Instruction exception when the coprocessor instruction is executed.


To access the CNTENC Register, read or write CP15 with:

MRC p15, 0, <Rd>, c9, c12, 2 ; Read CNTENC Register
MCR p15, 0, <Rd>, c9, c12, 2 ; Write CNTENC Register

You can use the enable, EN, bit [0] of the PMNC Register to disable all performance counters including CCNT. The CNTENC Register retains its value when the enable bit of the PMNC is set to 0, even though its settings are ignored.

Copyright © 2006-2009 ARM Limited. All rights reserved.ARM DDI 0344I
Non-Confidential