3.2.5. c0, TLB Type Register

The purpose of the TLB Type Register is to return the number of lockable entries for both the instruction and data TLBs.

Each TLB has 32 entries organized as fully associative and lockable TLB.

The TLB Type Register is:

Figure 3.3 shows the bit arrangement of the TLB Type Register.

Figure 3.3. TLB Type Register format

Table 3.9 shows how the bit values correspond with the TLB Type Register functions.

Table 3.9. TLB Type Register bit functions




Reserved, Read-As-Zero (RAZ).



Instruction lockable size specifies the number of instruction TLB lockable entries:

0x20 = Processor has 32 lockable entries.



Data lockable size specifies the number of unified or data TLB lockable entries:

0x20 = Processor has 32 lockable entries.



Reserved, RAZ.



Unified specifies if the TLB is unified or if there are separate instruction and data TLBs:

0x1 = Processor has separate instruction and data TLBs.

Table 3.10 shows the results of attempted access for each mode.

Table 3.10. Results of access to the TLB Type Register[4]

Secure privilegedNonsecure privilegedSecure UserNonsecure User

[4] An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor instruction is executed.

To access the TLB Type Register, read CP15 with:

MRC p15, 0, <Rd>, c0, c0, 3  ; Read TLB Type Register
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