Undefined

Undefined

Undefined

Undefined

Software increment. The register is incremented only on writes to the Software Increment Register. See c9, Software Increment Register.

Instruction fetch that causes a refill at the lowest level of instruction or unified cache. Each instruction fetch from normal cacheable memory that causes a refill from outside of the cache is counted. Accesses that do not cause a new cache refill, but are satisfied from refilling data of a previous miss are not counted. Where instruction fetches consist of multiple instructions, these accesses count as single events. CP15 cache maintenance operations do not count as events. This counter increments for speculative instruction fetches and for fetches of instructions that reach execution.

Instruction fetch that causes a TLB refill at the lowest level of TLB. Each instruction fetch that causes a translation table walk or an access to another level of TLB caching is counted. CP15 TLB maintenance operations do not count as events. This counter increments for speculative instruction fetches and for fetches of instructions that reach execution.

Data read or write operation that causes a refill at the lowest level of data or unified cache. Each data read from or write to normal cacheable memory that causes a refill from outside of the cache is counted. Accesses that do not cause a new cache refill, but are satisfied from refilling data of a previous miss are not counted. Each access to a cache line to normal cacheable memory that causes a new linefill is counted, including the multiple transaction of instructions such as LDM or STM, PUSH and POP. Write-through writes that hit in the cache do not cause a linefill and so are not counted. CP15 cache maintenance operations do not count as events. This counter increments for speculative data accesses and for data accesses that are explicitly made by instructions.

Data read or write operation that causes a cache access at the lowest level of data or unified cache. Each access to a cache line to normal cacheable memory is counted including the multiple transaction of instructions such as LDM or STM. CP15 cache maintenance operations do not count as events. This counter increments for speculative data accesses and for data accesses that are explicitly made by instructions.

Data read or write operation that causes a TLB refill at the lowest level of TLB. Each data read or write operation that causes a translation table walk or an access to another level of TLB caching is counted. CP15 TLB maintenance operations do not count as events. This counter increments for speculative data accesses and for data accesses that are explicitly made by instructions.

Data read architecturally executed. This counter increments for every instruction that explicitly read data, including SWP. This counter only increments for instructions that are unconditional or that pass their condition codes.

Data write architecturally executed. The counter increments for every instruction that explicitly wrote data, including SWP. This counter only increments for instructions that are unconditional or that pass their condition codes.

Instruction architecturally executed. This counter counts for all instructions, including conditional instructions that fail their condition codes.

Exception taken. This counts for each exception taken.

Exception return architecturally executed. This includes:

This counter only increments for instructions that are unconditional or that pass their condition codes.

Instruction that writes to the Context ID Register architecturally executed. This counter only increments for instructions that are unconditional or that pass their condition codes.

Software change of PC, except by an exception, architecturally executed. This counter only increments for instructions that are unconditional or that pass their condition codes.

Immediate branch architecturally executed, taken or not taken. This includes B{L}, BLX, CB{N}Z, HB{L}, and HBLP. This counter counts for all immediate branch instructions that are architecturally executed, including conditional instructions that fail their condition codes.

Procedure return, other than exception returns, architecturally executed. This includes:

This counter only increments for instructions that are unconditional or that pass their condition codes.

Unaligned access architecturally executed. This counts each instruction that is an access to an unaligned address. This counter only increments for instructions that are unconditional or that pass their condition codes.

Branch mispredicted or not predicted. This counts for every pipeline flush because of a misprediction from the program flow prediction resources.

Cycle count. This counts for every clock cycle.

Branches or other change in the program flow that could have been predicted by the branch prediction resources of the processor.

Reserved.

Any write buffer full cycle.

Any store that is merged in the L2 memory system.

Any bufferable store transaction from load/store to L2 cache, excluding eviction or cast out data.

Any accesses to the L2 cache.

Any cacheable miss in the L2 cache.

The number of AXI read data packets.

The number of AXI write data packets.

Any replay event in the memory system.

Any unaligned memory access that results in a replay.

Any L1 data memory access that misses in the cache as a result of the hashing algorithm. The cases covered are:

Any L1 instruction memory access that misses in the cache as a result of the hashing algorithm. The cases covered are:

Any L1 data memory access in which a page coloring alias occurs.

alias = virtual address [12] ! = physical address [12]

This behavior results in a data memory eviction or cast out.

Any NEON access that hits in the L1 data cache.

Any NEON cacheable data accesses for L1 data cache.

Any L2 cache accesses as a result of a NEON memory access.

Any NEON hit in the L2 cache.

Any L1 instruction cache access, excluding CP15 cache accesses.

Any return stack misprediction because of incorrect target address for a taken return stack pop.

Two forms of branch direction misprediction:

Any predictable branch that is predicted to be taken.

Any predictable branch that is executed and taken.

Number of operations issued, where an operation is either:

Increment for every cycle that no instructions are available for issue.

For every cycle, this event counts the number of instructions issued in that cycle. Multi-cycle instructions are only counted once.

Number of cycles the processor stalls waiting on MRC data from NEON.

Number of cycles that the processor stalls as a result of a full NEON instruction queue or NEON load queue.

Number of cycles that NEON and integer processors are both not idle.

Reserved.

Counts any event from external input source PMUEXTIN[0].

Counts any event from external input source PMUEXTIN[1].

Counts any event from both external input sources PMUEXTIN[0] and PMUEXTIN[1].

Reserved.