3.2.49. c9, Event Selection Register

The purpose of the Event SELection (EVTSEL) Register is to select the events that you want a Performance Monitor Count Register to count.

The EVTSEL Register is:

Figure 3.44 shows the bit arrangement of the EVTSEL Register.

Figure 3.44. Event Selection Register format


Table 3.95 shows how the bit values correspond with the EVTSEL Register functions.

Table 3.95. Event Selection Register bit functions

BitsFieldFunction
[31:8]-Reserved. RAZ, SBZP
[7:0]SELSpecifies the event selected as shown in Table 3.97

Table 3.96 shows the results of attempted access for each mode.

Table 3.96. Results of access to the Event Selection Register[40]

 

Secure privileged

Nonsecure privileged

Secure User

Nonsecure User

EN[1]ReadWriteReadWriteReadWriteReadWrite
0DataDataDataData

Undefined

Undefined

Undefined

Undefined

1DataDataDataDataDataDataDataData

[40] An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor instruction is executed.

[1] The EN bit in c9, User Enable Register enables User mode access of the Performance Monitor Registers.


To access the EVTSEL Register, read or write CP15 with:

MRC p15, 0, <Rd>, c9, c13, 1 ; Read EVTSEL Register
MCR p15, 0, <Rd>, c9, c13, 1 ; Write EVTSEL Register

Table 3.97 shows the range values for predefined events that you can monitor using the EVTSEL Register.

Table 3.97. Values for predefined events

ValueDescription
0x00

Software increment. The register is incremented only on writes to the Software Increment Register. See c9, Software Increment Register.

0x01

Instruction fetch that causes a refill at the lowest level of instruction or unified cache. Each instruction fetch from normal cacheable memory that causes a refill from outside of the cache is counted. Accesses that do not cause a new cache refill, but are satisfied from refilling data of a previous miss are not counted. Where instruction fetches consist of multiple instructions, these accesses count as single events. CP15 cache maintenance operations do not count as events. This counter increments for speculative instruction fetches and for fetches of instructions that reach execution.

0x02

Instruction fetch that causes a TLB refill at the lowest level of TLB. Each instruction fetch that causes a translation table walk or an access to another level of TLB caching is counted. CP15 TLB maintenance operations do not count as events. This counter increments for speculative instruction fetches and for fetches of instructions that reach execution.

0x03

Data read or write operation that causes a refill at the lowest level of data or unified cache. Each data read from or write to normal cacheable memory that causes a refill from outside of the cache is counted. Accesses that do not cause a new cache refill, but are satisfied from refilling data of a previous miss are not counted. Each access to a cache line to normal cacheable memory that causes a new linefill is counted, including the multiple transaction of instructions such as LDM or STM, PUSH and POP. Write-through writes that hit in the cache do not cause a linefill and so are not counted. CP15 cache maintenance operations do not count as events. This counter increments for speculative data accesses and for data accesses that are explicitly made by instructions.

0x04

Data read or write operation that causes a cache access at the lowest level of data or unified cache. Each access to a cache line to normal cacheable memory is counted including the multiple transaction of instructions such as LDM or STM. CP15 cache maintenance operations do not count as events. This counter increments for speculative data accesses and for data accesses that are explicitly made by instructions.

0x05

Data read or write operation that causes a TLB refill at the lowest level of TLB. Each data read or write operation that causes a translation table walk or an access to another level of TLB caching is counted. CP15 TLB maintenance operations do not count as events. This counter increments for speculative data accesses and for data accesses that are explicitly made by instructions.

0x06

Data read architecturally executed. This counter increments for every instruction that explicitly read data, including SWP. This counter only increments for instructions that are unconditional or that pass their condition codes.

0x07

Data write architecturally executed. The counter increments for every instruction that explicitly wrote data, including SWP. This counter only increments for instructions that are unconditional or that pass their condition codes.

0x08

Instruction architecturally executed. This counter counts for all instructions, including conditional instructions that fail their condition codes.

0x09

Exception taken. This counts for each exception taken.

0x0A

Exception return architecturally executed. This includes:

  • RFE <addressing_mode> <Rn>{!}

  • MOVS PC (and other similar data processing instructions)

  • LDM <addressing_mode> Rn{!}, <registers_and_pc>

This counter only increments for instructions that are unconditional or that pass their condition codes.

0x0B

Instruction that writes to the Context ID Register architecturally executed. This counter only increments for instructions that are unconditional or that pass their condition codes.

0x0C

Software change of PC, except by an exception, architecturally executed. This counter only increments for instructions that are unconditional or that pass their condition codes.

0x0D

Immediate branch architecturally executed, taken or not taken. This includes B{L}, BLX, CB{N}Z, HB{L}, and HBLP. This counter counts for all immediate branch instructions that are architecturally executed, including conditional instructions that fail their condition codes.

0x0E

Procedure return, other than exception returns, architecturally executed. This includes:

  • BX R14

  • MOV PC, LR

  • POP {..., PC}

  • LDR PC, [R13], #offset

  • LDMIA R9!, {...,PC}

  • LDR PC, [R9], #offset

This counter only increments for instructions that are unconditional or that pass their condition codes.

0x0F

Unaligned access architecturally executed. This counts each instruction that is an access to an unaligned address. This counter only increments for instructions that are unconditional or that pass their condition codes.

0x10

Branch mispredicted or not predicted. This counts for every pipeline flush because of a misprediction from the program flow prediction resources.

0x11

Cycle count. This counts for every clock cycle.

0x12

Branches or other change in the program flow that could have been predicted by the branch prediction resources of the processor.

0x13-0x3F

Reserved.

0x40

Any write buffer full cycle.

0x41

Any store that is merged in the L2 memory system.

0x42

Any bufferable store transaction from load/store to L2 cache, excluding eviction or cast out data.

0x43

Any accesses to the L2 cache.

0x44

Any cacheable miss in the L2 cache.

0x45

The number of AXI read data packets.

0x46

The number of AXI write data packets.

0x47

Any replay event in the memory system.

0x48

Any unaligned memory access that results in a replay.

0x49

Any L1 data memory access that misses in the cache as a result of the hashing algorithm. The cases covered are:

  • hash hit and physical address miss

  • hash hit and physical address hit in another way

  • hash miss and physical address hit.

0x4a

Any L1 instruction memory access that misses in the cache as a result of the hashing algorithm. The cases covered are:

  • hash hit and physical address miss

  • hash hit and physical address hit in another way

  • hash miss and physical address hit.

0x4b

Any L1 data memory access in which a page coloring alias occurs.

alias = virtual address [12] ! = physical address [12]

This behavior results in a data memory eviction or cast out.

0x4c

Any NEON access that hits in the L1 data cache.

0x4d

Any NEON cacheable data accesses for L1 data cache.

0x4e

Any L2 cache accesses as a result of a NEON memory access.

0x4f

Any NEON hit in the L2 cache.

0x50

Any L1 instruction cache access, excluding CP15 cache accesses.

0x51

Any return stack misprediction because of incorrect target address for a taken return stack pop.

0x52

Two forms of branch direction misprediction:

  • branch predicted taken, but was not taken

  • branch predicted not taken, but was taken.

0x53

Any predictable branch that is predicted to be taken.

0x54

Any predictable branch that is executed and taken.

0x55

Number of operations issued, where an operation is either:

  • an instruction

  • one operation in a sequence of operations that make up a multi-cycle instruction.

0x56

Increment for every cycle that no instructions are available for issue.

0x57

For every cycle, this event counts the number of instructions issued in that cycle. Multi-cycle instructions are only counted once.

0x58

Number of cycles the processor stalls waiting on MRC data from NEON.

0x59

Number of cycles that the processor stalls as a result of a full NEON instruction queue or NEON load queue.

0x5a

Number of cycles that NEON and integer processors are both not idle.

0x60-0x6F

Reserved.

0x70

Counts any event from external input source PMUEXTIN[0].

0x71

Counts any event from external input source PMUEXTIN[1].

0x72

Counts any event from both external input sources PMUEXTIN[0] and PMUEXTIN[1].

0x73-0xFF

Reserved.


If this unit generates an interrupt, the processor asserts the pin nPMUIRQ. You can route this pin to an external interrupt controller for prioritization and masking. This is the only mechanism that signals this interrupt to the core.

The absolute counts recorded might vary because of pipeline effects. This has negligible effect except in cases where the counters are enabled for a very short time.

In addition to the counters within the processor, most of the events that Table 3.97 shows are available to the ETM unit or other external trace hardware to enable the events to be monitored. See Chapter 14 Embedded Trace Macrocell and Chapter 15 Cross Trigger Interface for more information.

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