3.2.75. c15, L1 TLB operations

The purpose of the L1 TLB operations is to:

The L1 TLB operations are accessible in secure privileged modes only.

Figure 3.69 shows the bit arrangement of the L1 TLB CAM read operations.

Figure 3.69. L1 TLB CAM read operation format


Figure 3.70 shows the bit arrangement of the L1 TLB CAM write operations.

Figure 3.70. L1 TLB CAM write operation format


TLB CAM array examples

To write one entry in data side TLB CAM array, for example:

LDR R0, =0x03000323;            
MCR p15, 0, R0, c15, c0, 0;     Move R0 to D-L1 Data 0 Register
LDR R2, =0x01;                  
MCR p15, 0, R2, c15, c0, 1;     Move R0 to D-L1 Data 1 Register
LDR R1, =0x00C00000;            
MCR p15, 0, R1, c15, c0, 2;     Write D-L1 Data 0 or 1 Register to D-TLB CAM

To read one entry in data side TLB CAM array, for example:

LDR R1, =0x00C00000;            
MCR p15, 0, R1, c15, c2, 2;     Read D-TLB CAM into data L1 Data 0/1 Register
MRC p15, 0, R0, c15, c0, 0;     Move D-L1 Data 0 Register to R0
MRC p15, 0, R2, c15, c0, 1;     Move D-L1 Data 1 Register to R2

To write one entry in instruction side TLB CAM array, for example:

LDR R0, =0x03000323;            
MCR p15, 0, R0, c15, c1, 0;     Move R0 to I-L1 Data 0 Register
LDR R2, =0x01;                  
MCR p15, 0, R2, c15, c1, 1;     Move R0 to I-L1 Data 1 Register
LDR R1, =0x00C00000;            
MCR p15, 0, R1, c15, c1, 2;     Write I-L1 Data 0 or 1 Register to D-TLB CAM

To read one entry in instruction side TLB CAM array, for example:

LDR R1, =0x00C00000;            
MCR p15, 0, R1, c15, c3, 2;     Read I-TLB CAM into data L1 Data 0/1 Register
MRC p15, 0, R0, c15, c1, 0;     Move I-L1 Data 0 Register to R0
MRC p15, 0, R2, c15, c1, 1;     Move I-L1 Data 1 Register to R2

TLB ATTR array examples

To write one entry in data side TLB ATTR array, for example:

LDR R0, =0x252E;                
MCR p15, 0, R0, c15, c0, 0;     Move R0 to D-L1 Data 0 Register
LDR R1, =0x00C00000;            
MCR p15, 0, R1, c15, c0, 3;     Write D-L1 Data 0 Register to D-TLB ATTR

To read one entry in data side TLB ATTR array, for example:

LDR R1, =0x00C00000;            
MCR p15, 0, R1, c15, c2, 3;     Read D-TLB ATTR into data L1 Data 0 Register
MRC p15, 0, R0, c15, c0, 0;     Move D-L1 Data 0 Register to R0

To write one entry in instruction side TLB ATTR array, for example:

LDR R0, =0x252E;                
MCR p15, 0, R0, c15, c1, 0;     Move R0 to I-L1 Data 0 Register
LDR R1, =0x00C00000;            
MCR p15, 0, R1, c15, c1, 3;     Write I-L1 Data 0 Register to I-TLB ATTR

To read one entry in instruction side TLB ATTR array, for example:

LDR R1, =0x00C00000;            
MCR p15, 0, R1, c15, c3, 3;     Read I-TLB ATTR into data L1 Data 0 Register
MRC p15, 0, R0, c15, c0, 0;     Move I-L1 Data 0 Register to R0

TLB PA array examples

To write one entry in data side TLB PA array, for example:

LDR R0, =0x05730000;            
MCR p15, 0, R0, c15, c0, 0;     Move R0 to D-L1 Data 0 Register
LDR R1, =0x00C00000;            
MCR p15, 0, R1, c15, c0, 4;     Write D-L1 Data 0 Register to D-TLB PA

To read one entry in data side TLB PA array, for example:

LDR R1, =0x00C00000;            
MCR p15, 0, R1, c15, c2, 4;     Read D-TLB PA into data L1 Data 0 Register
MRC p15, 0, R0, c15, c0, 0;     Move D-L1 Data 0 Register to R0

To write one entry in instruction side TLB PA array, for example:

LDR R0, =0x05730000;            
MCR p15, 0, R0, c15, c1, 0;     Move R0 to I-L1 Data 0 Register
LDR R1, =0x00C00000;            
MCR p15, 0, R1, c15, c1, 4;     Write I-L1 Data 0 Register to I-TLB PA

To read one entry in instruction side TLB PA array, for example:

LDR R1, =0x00C00000;            
MCR p15, 0, R1, c15, c3, 4;     Read I-TLB PA into data L1 Data 0 Register
MRC p15, 0, R0, c15, c1, 0;     Move I-L1 Data 0 Register to R0
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