3.2.66. c11, PLE Channel Status Register

The purpose of the PLE Channel Status Register for each channel is to define the status of the most recently started PLE operation on that channel.

The PLE Channel Status Register is:

Figure 3.59 shows the bit arrangement of the PLE Channel Status Register.

Figure 3.59. PLE Channel Status Register format


Table 3.132 shows how the bit values correspond with the PLE Channel Status Register functions.

Table 3.132. PLE Channel Status Register bit functions

BitsFieldFunction
[31:9]-

Reserved. UNP, SBZ.

[8:2]Error code

Indicates the status of the external address error. All other encodings are reserved:

b0xxxxxx = no error

b1x01100 = precise external abort, L1 translation

b1x01110 = precise external abort, L2 translation

b1011100 = parity/ECC error on L1 translation

b1011110 = parity/ECC error on L2 translation

b1000101 = translation fault, section

b1000111 = translation fault, page

b1000011 = access flag fault, section

b1000110 = access flag fault, page

b1001001 = domain fault, section

b1001011 = domain fault, page

b1001101 = permission fault, section

b1001111 = permission fault, page

b1x10110 = imprecise external abort

b1011000 = imprecise parity or ECC error, nontranslation.

Any unused encoding not listed is reserved.

Where x represents bit [7] in the encoding, bit [7] can be either:

0 = AXI Decode error caused the abort, reset value

1 = AXI Slave error caused the abort.

[1:0]Status

Indicates the status of the PLE channel:

b00 = idle, reset value

b01 = reserved

b10 = running

b11 = complete or error.


Access in the Nonsecure state depends on the PLE bit, see c1, Nonsecure Access Control Register. You can access these registers in User mode if the U bit for the currently selected channel is set to 1, see c11, PLE User Accessibility Register.

Table 3.133 shows the results of attempted access for each mode.

Table 3.133. Results of access to the PLE Channel Status Register[55]

  Secure privilegedNonsecure privilegedSecure UserNonsecure User
U bitPLE bitReadWriteReadWriteReadWriteReadWrite
00DataUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefined
1DataUndefinedDataUndefinedUndefinedUndefinedUndefinedUndefined
10DataUndefinedUndefinedUndefinedDataUndefinedUndefinedUndefined
1DataUndefinedDataUndefinedDataUndefinedDataUndefined

[55] An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor instruction is executed.


To access the PLE Channel Status Register, set PLE Channel Number Register to the appropriate PLE channel and read CP15 with:

MRC p15, 0, <Rd>, c11, c8, 0 ; Read PLE Channel Status Register

For more details on the operation of the L2 PreLoad Engine (PLE), see L2 PLE.

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