3.2.62. c11, PLE enable commands

The purpose of the PLE enable commands is to start, stop, or clear PLE transfers for each channel implemented.

The PLE enable commands are:

Access in the Nonsecure state depends on the PLE bit, see c1, Nonsecure Access Control Register. The processor can access these commands in User mode if the U bit, see c11, PLE User Accessibility Register, for the currently selected channel is set to 1.

Table 3.125 shows the results of attempted access for each mode.

Table 3.125. Results of access to the PLE enable commands[51]

  Secure privilegedNonsecure privilegedSecure UserNonsecure User
U bit PLE bitReadWriteReadWriteReadWriteReadWrite
00UndefinedDataUndefinedUndefinedUndefinedUndefinedUndefinedUndefined
1UndefinedDataUndefinedDataUndefinedUndefinedUndefinedUndefined
10UndefinedDataUndefinedUndefinedUndefinedDataUndefinedUndefined
1UndefinedDataUndefinedDataUndefinedDataUndefinedData

[51] An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor instruction is executed.


To issue a PLE enable command, set the PLE Channel Number Register to the appropriate PLE channel and execute one of the following CP15 command:

MCR p15, 0, <Rd>, c11, c3, 0 ; Stop PLE enable command
MCR p15, 0, <Rd>, c11, c3, 1 ; Start PLE enable command
MCR p15, 0, <Rd>, c11, c3, 2 ; Clear PLE enable command
Copyright © 2006-2009 ARM Limited. All rights reserved.ARM DDI 0344I
Non-Confidential