9.2.1. AXI identifiers

The AXI interconnect uses identifiers with each transaction that enables requests to be serviced out-of-order under certain circumstances. The processor supports multiple outstanding transactions and assigns unique IDs to each specific transaction. There are two sets of identifiers, one for the read address channel, ARRID[3:0], and one for the write address channel, AWRID[3:0]. Table 9.1 shows the AXI ID assignment for read address channel.

Table 9.1. Read address channel AXI ID

Read address channel request typeID tag value
Instruction fetchL2 cacheableb1000-b1011
L1 cacheable (L2 non-cacheable)b1111
Noncacheable or Strongly Orderedb0100
Shared or nonshared deviceb0101
Integer data and CP14 loadsL2 cacheableb1000-b1011
L1 cacheable (L2 non-cacheable)b1110
Noncacheable or Strongly Orderedb0000
Shared deviceb0001
Nonshared deviceb0011
NEON and VFP loadsL2 cacheableb1000-b1011
Noncacheable or Strongly Orderedb0000
Shared deviceb0001
Nonshared deviceb0011
Table WalksL2 cacheableb1000-b1011
Noncacheableb0110
PLD and PLEL2 cacheableb1000-b1011

Table 9.2 shows the AXI ID assignment for write address channel.

Table 9.2. Write address channel AXI ID

Write address channel request typeID tag value
Evictions from L2 cacheEach ID corresponds to one eviction in the L2 cacheb1000 - b1011
Integer data and CP14 writes

Noncacheable/cacheable

Write-through/strongly ordered

b0000
Cacheable non-burst writesb0010
Shared deviceb0001
Nonshared deviceb0011
NEON and VFP writes

Noncacheable/cacheable

Write-through/strongly ordered

b0000
Cacheable non-burst writesb0010
Shared deviceb0001
Nonshared deviceb0011
PLEL2 cacheableb1000-b1011
CP15 (cache maintenance)L2 cacheableb1000-b1011

The processor supports multiple read and write channel transactions as Table 9.3 shows.

Table 9.3. AXI master interface attributes

AttributeOutstanding transactions
Write Issuing Capability12
Read Issuing Capability18
Combined Issuing Capability26[1]

[1] The combined issuing capability is limited to a total of four outstanding linefills or evictions. Therefore the sum of the read and write issuing capability does not equal the combined issuing capability.


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