9.4.2. Evictions

To reduce the number of burst transfers on the AXI interface, a subset of the cache line is written only if it is partially dirty. The burst size depends on the bus configuration and which quadwords of the cache line contain dirty data.

The CortexA8 processor contains four dirty bits per 64 byte cache line, representing four 128-bit packets of data, or four quadwords of data. The encoding of the dirty bits defines the number, or length, of transfers on the AWLEN[3:0] signals. Table 9.6 shows the different possible evictions that can take place for all combinations of dirty bits.

Table 9.6. Number of transfers on AXI write channel for an eviction

Quadword Dirty Bit[3:0]128-bit AXI AWLEN[3:0]64-bit AXI AWLEN[3:0]
b0000No evictionNo eviction
b0001b0000b0001
b0010b0000b0001
b0011b0001b0011
b0100b0000 b0001
b0101b0010b0101
b0110b0001b0011
b0111b0010b0101
b1000b0000b0001
b1001b0011b0111
b1010b0010b0101
b1011b0011b0111
b1100b0001 b0011
b1101 b0011 b0111
b1110b0010b0101
b1111b0011b0111

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