15.2. Trigger inputs and outputs

This section describes the trigger inputs and outputs that are available to the CTI.

Table 15.1 shows the trigger inputs available to the CTI.

Table 15.1. Trigger inputs

Trigger inputNameClock domainDescription
0Debug entry[1]CLKPulsedon entry to debug state
1!nPMUIRQCLKPMU generated interrupt
2EXTOUT[0]CLKETM external output
3EXTOUT[1]CLKETM external output
4COMMRXCLKDebug communication receive channel is full
5COMMTXCLKDebug communication transmit channel is empty
6TRIGGERATCLKETM trigger

[1] For revision r3 of the Cortex-A8 processor, this trigger is a pulse asserted on debug state entry. For revisions r0 through r2, this trigger is a level-sensitive signal asserted while the processor is in debug state. This level-sensitive signal is DBGTRIGGER.


Table 15.2 shows the trigger outputs available to the CTI.

Table 15.2. Trigger outputs

Trigger OutputNameClock domainEdge detection enableDescription
0EDBGRQCLK-Causes the processor to enter debug state.
1EXTIN[0]CLKASICCTL[0]ETM external input.
2EXTIN[1]CLKASICCTL[1]ETM external input.
3EXTIN[2]CLKASICCTL[2]ETM external input.
4EXTIN[3]CLKASICCTL[3]ETM external input.
5PMUEXTIN[0]CLKASICCTL[4]PMU CTI event. This input can be selected by the Event Selection Register. See c9, Event Selection Register for more information on PMU events.
6PMUEXTIN[1]CLKASICCTL[5]PMU CTI event. This input can be selected by the Event Selection Register. See c9, Event Selection Register for more information on PMU events.
7DBGRESTARTCLK-Causes the processor to exit debug state.
8!nCTIIRQAsynchronous-Generates an interrupt if nCTIIRQ is connected appropriately to the interrupt controller.

Note

  • In revision r3 of the Cortex-A8 processor, trigger outputs 0 and 8 must be cleared by software. See CTI Interrupt Acknowledge Register, CTIINTACK.

  • In revisions r0 through r2, only trigger output 8 must be cleared by software. Trigger output 0 is automatically cleared by the debug state entry event.

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