1.3.4. Load/store

The load/store unit encompasses the entire L1 data side memory system and the integer load/store pipeline. This includes:

The pipeline accepts one load or store per cycle that can be present in either pipeline 0 or pipeline 1. This gives the processor flexibility when scheduling load and store instructions. See Chapter 7 Level 1 Memory System for more information.

Copyright © 2006-2009 ARM Limited. All rights reserved.ARM DDI 0344I