15.8.4. Peripheral Identification Registers

The CTI Peripheral Identification Registers are a set of eight read-only registers, PeripheralID7 to PeripheralID0. Only bits [7:0] of each register are used.

Table 15.30 shows the bit field definitions of the Peripheral Identification Registers. The CoreSight Architecture Specification describes many of these fields in more detail.

Table 15.30. Peripheral Identification Registers bit functions

Register nameOffsetBitsValueFunction
PeripheralID70xFDC[31:8]-Unused, RAZ
  [7:0]0x00Reserved for future use, RAZ
PeripheralID60xFD8[31:8]-Unused, RAZ
  [7:0]0x00Reserved for future use, RAZ
PeripheralID50xFD4[31:8]-Unused, RAZ
  [7:0]0x00Reserved for future use, RAZ
PeripheralID40xFD0[31:8]-Unused, RAZ
  [7:4]0x0Indicates that the ETM uses one 4KB block of memory
  [3:0]0x4JEP106 continuation code [3:0]
PeripheralID30xFEC[31:8]-Unused, RAZ
  [7:4]0x1RevAnd (at top level)
  [3:0]0x0Customer Modified 0x00 indicates from ARM
PeripheralID20xFE8[31:8]-Unused, RAZ
  [7:4]0x6Revision number of Peripheral
  [3]0x1Indicates that a JEDEC assigned value is used
  [2:0]0x3JEP106 identity code [6:4]
PeripheralID10xFE4[31:8]-Unused, RAZ
  [7:4]0xBJEP106 identity code [3:0]
  [3:0]0x9Part number 1 upper Binary Coded Decimal (BCD) value of Device number
PeripheralID00xFE0[31:8]-Unused, RAZ
  [7:0]0x22Part number 0 middle and lower BCD value of Device number

Note

In Table 15.30, the Peripheral Identification Registers are listed in order of register name, from most significant (ID7) to least significant (ID0). This does not match the order of the register offsets. Similarly, in Table 15.31, the Component Identification Registers are listed in order of register name, from most significant (ID3) to least significant (ID0).

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